TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.4.19 Distributed Clocks LATCH In Unit
6.4.19.1 Latch0 Control (0x09A8)
Bit
Description
ECAT
PDI
Reset Value
0
Latch0 positive edge:
r/(w)
r/(w)
0
0: Continuous Latch active
1: Single event (only first event active)
1
Latch0 negative edge:
0: Continuous Latch active
1: Single event (only first event active)
r/(w)
r/-
r/(w)
r/-
0
0
7:2
Reserved, write 0
Table 109: Register 0x09A8 (Latch0 Control)
Note
Write access depends upon setting of 0x0980.4.
6.4.19.2 Latch1 Control (0x09A9)
Bit
Description
ECAT
PDI
Reset Value
0
Latch1 positive edge:
r/(w)
r/(w)
0
0: Continuous Latch active
1: Single event (only first event active)
1
Latch01 negative edge:
0: Continuous Latch active
1: Single event (only first event active)
r/(w)
r/-
r/(w)
r/-
0
0
7:2
Reserved, write 0
Table 110: Register 0x09A9 (Latch1 Control)
Note
Write access depends upon setting of 0x0980.5.
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