TMC5161 DATASHEET (Rev. 1.01 / 2018-NOV-20)
30
GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
Register
Description / bit names
Bit SLAVECONF
7..0 SLAVEADDR:
These eight bits set the address of unit for the UART
interface. The address becomes incremented by one
when the external address pin NEXTADDR is active.
Range: 0-253 (254 cannot be incremented), default=0
8
+
11..8 SENDDELAY:
0, 1: 8 bit times (not allowed with multiple slaves)
W
0x03
SLAVECONF
4
2, 3:
4, 5:
6, 7:
8, 9:
3*8 bit times
5*8 bit times
7*8 bit times
9*8 bit times
10, 11: 11*8 bit times
12, 13: 13*8 bit times
14, 15: 15*8 bit times
INPUT
Bit
Reads the state of all input pins available
0 REFL_STEP
1 REFR_DIR
2 ENCB_DCEN_CFG4
3 ENCA_DCIN_CFG5
4 DRV_ENN
5 ENC_N_DCO_CFG6
6 SD_MODE (1=External step and dir source)
8
+
8
R
0x04
IOIN
7 SWCOMP_IN (Shows voltage difference of SWN and
SWP. Bring DIAG outputs to high level with pushpull
disabled to test the comparator.)
31.. VERSION: 0x30=first version of the IC
24 Identical numbers mean full digital compatibility.
Bit
OUTPUT
Sets the IO output pin polarity in UART mode
0
In UART mode, SDO_CFG0 is an output. This bit
programs the output polarity of this pin. Its main
purpose it to use SDO_CFG0 as NAO next address
output signal for chain addressing of multiple ICs.
Hint: Reset Value is 1 for use as NAO to next IC in
single wire chain
W
0x04
1
OUTPUT
Position comparison register for motion controller position
strobe. The Position pulse is available on output SWP_DIAG1.
W
W
0x05
0x06
32 X_COMPARE
XACTUAL = X_COMPARE:
-
Output signal PP (position pulse) becomes high. It
returns to a low state, if the positions mismatch.
OTP_PROGRAM – OTP programming
Bit
Write access programs OTP memory (one bit at a time),
Read access refreshes read data from OTP after a write
2..0 OTPBIT
Selection of OTP bit to be programmed to the selected
byte location (n=0..7: programs bit n to a logic 1)
5..4 OTPBYTE
Set to 00
OTP_PROG
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