TMC5161 DATASHEET (Rev. 1.01 / 2018-NOV-20)
33
6.1.1 OTP_READ – OTP configuration memory
The OTP memory holds power up defaults for certain registers. All OTP memory bits are cleared to 0
by default. Programming only can set bits, clearing bits is not possible. Factory tuning of the clock
frequency affects otp0.0 to otp0.4. The state of these bits therefore may differ between individual ICs.
0X07: OTP_READ – OTP MEMORY MAP
Bit Name
Function
Comment
7
6
5
otp0.7
otp0.6
otp0.5
otp_TBL
Reset default for TBL:
0: TBL=%10 (~3µs)
1: TBL=%01 (~2µs)
Reset default for DRVCONF.BBMCLKS
0: BBMCLKS=4
1: BBMCLKS=2 Default – cannot be changed!
Reset default for Short detection Levels:
0: S2G_LEVEL = S2VS_LEVEL = 6
1: S2G_LEVEL = S2VS_LEVEL = 12 Default - cannot be
changed!
otp_BBM
otp_S2_LEVEL
4
3
2
1
0
otp0.4
otp0.3
otp0.2
otp0.1
otp0.0
OTP_FCLKTRIM
Reset default for FCLKTRIM
0: lowest frequency setting
31: highest frequency setting
Attention: This value is pre-programmed by factory clock
trimming to the default clock frequency of 12MHz and
differs between individual ICs! It should not be altered.
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