TMC5160 DATASHEET (Rev. 1.08 / 2018-NOV-19)
12
2.2 Signal Descriptions
Pin
TQFP QFN
Type Function
High side gate driver output.
Bootstrap capacitor positive connection.
HB1
CB1
1
2
2
3
Output of internal 11.5V gate voltage regulator and supply pin
of low side gate drivers. Attach 2.2µF to 10µF ceramic
capacitor to GND plane near to pin for best performance. Use
at least 10 times more capacity than for bootstrap capacitors.
In case an external gate voltage supply is available, tie VSA
and 12VOUT to the external supply.
12VOUT
VSA
3
4
4
5
Analog supply voltage for 11.5V and 5V regulator. Normally
tied to VS. Provide a 100nF filtering capacitor.
Output of internal 5V regulator. Attach 2.2µF to 10µF ceramic
capacitor to GNDA near to pin for best performance. Output
for VCC supply of the chip.
5VOUT
GNDA
SRAL
5
6
7
6
7
8
Analog GND. Connect to GND plane near pin.
Sense resistor GND connection for phase A. Connect to the
GND side of the sense resistor in order to compensate for
voltage drop on the GND interconnection.
Sense resistor for phase A. Connect to the upper side of the
sense resistor. A Kelvin connection is preferred with high
motor currents. Symmetrical RC-Filtering may be added for
SRAL and SRAH to eliminate high frequency switching spikes
from other drives or switching of coil B.
Sense resistor for phase B. Connect to the upper side of the
sense resistor. A Kelvin connection is preferred with high
motor currents. Symmetrical RC-Filtering may be added for
SRBL and SRBH to eliminate high frequency switching spikes
from other drives or switching of coil A.
AI
AI
SRAH
SRBH
8
9
9
10
AI
Sense resistor GND connection for phase B. Connect to the
GND side of the sense resistor in order to compensate for
voltage drop on the GND interconnection.
SRBL
10
11
12
11
12
13
AI
DI
DI
TST_MODE
CLK
Test mode input. Tie to GND using short wire.
CLK input. Tie to GND using short wire for internal clock or
supply external clock. Internal clock-fail over circuit protects
against loss of external clock signal.
SPI chip select input (negative active) (SPI_MODE=1) or
Configuration input (SPI_MODE=0)
SPI serial clock input (SPI_MODE=1) or
CSN_CFG3
SCK_CFG2
13
14
14
15
DI
DI
Configuration input (SPI_MODE=0)
SPI data input (SPI_MODE=1) or
SDI_CFG1
SDO_CFG0
15
16
16
17
DI
Configuration input (SPI_MODE=0) or
Next address input (NAI) for single wire interface.
SPI data output (tristate) (SPI_MODE=1) or
Configuration input (SPI_MODE=0) or
DIO
Next address output (NAO) for single wire interface.
Left reference input (for internal ramp generator) or
STEP input when (SD_MODE=1).
Right reference input (for internal ramp generator) or
DIR input (SD_MODE=1).
REFL_STEP
REFR_DIR
17
18
18
19
DI
DI
19,
30
20
25,
Pad
20
Digital GND. Connect to GND plane near pin.
GNDD
VCC_IO
3.3V to 5V IO supply voltage for all digital pins.
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