TMC4671 Datasheet • IC Version V1.00 | Document Revision V1.04 • 2018-Dec-11
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Address
Registername
2: ext. dsMOD with MCLK output
3: ext. dsMOD with ext. CMP
Name
Access
Mask
Type
Bool
Unit
0x00040000h
mclk_polarity_b
Min
0
Max
1
Default
0
0: Data is sampled on rising edge
1: Data is sampled on falling edge
Name
Mask
Type
Bool
Unit
0x00080000h
mdat_polarity_b
Min
0
Max
1
Default
0
0: MDAT is not inverted
1: MDAT is inverted
Mask
Name
Type
Bool
Unit
0x00100000h
sel_nclk_mclk_i_b
Min
0
Max
1
Default
0
0: MCLK is used (divided clock)
1: CLK (100 MHz) is used
Name
Mask
Type
0xFF000000h
blanking_b
Unsigned
Unit
Min
0
Max
Default
0
255
0x05h
dsADC_MCLK_A
Name
RW
Mask
Type
0xFFFFFFFFh
dsADC_MCLK_A
Max
Unsigned
Unit
Min
0
Default
4294967295 214748365
fMCLK_A = 231 / (fCLK * (dsADC_MCLK_A+1)), dsADC_MCLK_A =
(231 / (fMCLK * fCLK)) - 1
0x06h
dsADC_MCLK_B
RW
Mask
Name
dsADC_MCLK_B
Max
Type
0xFFFFFFFFh
Unsigned
Unit
Min
Default
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