TMC4330A Datasheet | Document Revision 1.01 • 2017-JAN-12
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Pin Description
Pin Names and Descriptions
Number Type Function
Pin
Supply Pins
6, 13,
22, 28
GND
GND Digital ground pin for IOs and digital circuitry.
VCC
5, 23, 29 VCC Digital power supply for IOs and digital circuitry (3.3V… 5V).
VDD1V8
14, 27
30
VDD Connection of internal generated core voltage of 1.8V.
Clock input to provide a clock with the frequency fCLK for all
CLK_EXT
I
internal operations.
Low active reset. If not connected, Power-on-Reset and internal
pull-up resistor is active.
NRST
31
26
I (PU)
I
TEST_MODE
Test mode input. Tie to low for normal operation.
Interface Pins for µC
NSCSIN
SCKIN
SDIIN
SDOIN
INTR
2
I
I
Low active chip selects input of SPI interface to µC.
Serial clock for SPI interface to µC.
3
4
I
Serial data input of SPI interface to µC.
7
O
O
O
Serial data output of SPI interface to µC (Z if NSCSIN=1).
Interrupt output, programmable PD/PU for wired-and/or.
Target reached output, programmable PD/PU for wired-and/or.
Reference Pins
25
TARGET_REACHED 24
Left stop switch. External signal to stop a ramp.
If not connected, internal pull-down resistor is active.
STOPL
10
11
12
15
I (PD)
I (PD)
I (PD)
I (PD)
Home reference signal input. External signal for reference search.
If not connected, internal pull-down resistor is active.
HOME_REF
STOPR
Right stop switch. External signal to stop a ramp.
If not connected, internal pull-down resistor is active.
Step input for external step control.
If not connected, internal pull-down resistor is active.
STPIN
Direction input for external step control.
If not connected, internal pull-down resistor is active.
DIRIN
START
16
17
I (PD)
IO
Start signal input/output.
S/D Output Pins
(Default: Output)
STPOUT
PWMA
Step output.
First PWM signal (Sine).
O
O
21
20
DIROUT
PWMB
Direction output.
Second PWM signal (Cosine).
Continued on next page!
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