Transcend 40-Pin IDE Flash Module
128MB ~ 8GB
Device Terminating an Ultra DMA Data-Out Burst
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing
diagram for the operation is shown in below: Ultra DMA Data-Out Burst Device Termination Timing. The
timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are
described in Page 13: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra
DMA data burst has been transferred.
(b) The device shall initiate Ultra DMA data burst termination by negating -DDMARDY.
(c) The host shall stop generating an HSTROBE edges within tRFS of the device negating -DDMARDY.
(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
device shall be prepared to receive zero, one, two or three additional data words. The additional
data words are a result of cable round trip delay and tRFS timing for the device.
(e) The device shall negate DMARQ no sooner than tRP after negating -DDMARDY. The device shall not
assert DMARQ again until after the Ultra DMA data burst is terminated.
(f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate
STOP again until after the Ultra DMA data burst is terminated.
(g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
(h) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA
CRC Calculation).
(i) The host shall negate -DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and -DDMARDY, and no sooner than tDVS after placing the result
of its CRC calculation on D[15:00].
(j) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(k) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one
command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC
Calculation).
(l) While operating in True IDE mode, the device shall release DSTROBE within tIORDYZ after the host
negates -DMACK.
(m) The host shall not negate STOP nor assert –HDMARDY until at least tACK after negating -DMACK.
(n) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least tACK after
negating DMACK.
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Transcend Information Inc.
Ver 1.7
TRANSCEND [ TRANSCEND INFORMATION. INC. ]
