TTP258
TonTouchTM
Preliminary
.PWM
The PWM period generated from TCP2. When PWMxEN (PWMC<0> or
PWMC<1> or PWMC<2>) enable, and PWMOUT pin (PA0, PA1, or PA2 the PAx
must be output mode and select normal IO by mask option) change to output
mode, PWMx signal will output to PWMOUT pin.
The duty of PWMx value is store in PWMxL and PWMxH, user write PWMxH
first, last write PWMxL. When write the PWMxL the 8 bits duty value will be
load to PWMxD at the same time. PWM’s duty value cannot bigger than TCP2
pre-load data. If not, PWMOUT is an unexpected signal.
User can select PWMOUT pin start with 1 or start with 0 by option. When
TCP2 enable, timer start increment, if timer/counter value bigger than PWM’s
duty value, PWMOUT will change state. The PWMOUT back to start state,
When TCP2 is overflow.
User does not use PWM in 16 bits timer/counter mode. If not, PWMOUT is
an unexpected signal.
User does not use TCP2D=00H. If not, PWMOUT is an unexpected signal.
PWMC[00EH]: PWM control register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
-
-
Bit2
PWM2EN
R/W
Bit1
PWM1EN
R/W
Bit0
PWM0EN
R/W
PWM0EN: PWM0 output enabled. (0: disable; 1: enable)
PWM1EN: PWM1 output enabled. (0: disable; 1: enable)
PWM2EN: PWM2 output enabled. (0: disable; 1: enable)
PWM0L[00FH]: PWM0 duty low nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM0D3
R/W
Bit2
PWM0D2
R/W
Bit1
PWM0D1
R/W
Bit0
PWM0D0
R/W
PWM0D3~0: PWM0 duty low nibble data
PWM0H[010H]: PWM0 duty high nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM0D7
R/W
Bit2
PWM0D6
R/W
Bit1
PWM0D5
R/W
Bit0
PWM0D4
R/W
PWM0D7~4: PWM0 duty high nibble data
PWM1L[01AH]: PWM1 duty low nibble data register[R/W], default value [----]
Register
Bit Name
Read/Write
Bit3
PWM1D3
R/W
Bit2
PWM1D2
R/W
Bit1
PWM1D1
R/W
Bit0
PWM1D0
R/W
PWM1D3~0: PWM1 duty low nibble data
16’/04/06
Page 25 of 44
Ver.: 1.2
TTELEC [ TT Electronics ]
