TTP258
TonTouchTM
Preliminary
.Counter
Counter feature is implemented only by TCPxLD=0, the TCPxD can be zero
or not that depends on software needs. User starts & stops the counter by
changing the TCPxEN bit value. On the save side, reading the counter value
after stopping the count by disable TCPxEN=0, if reading the counter value
during value changing that means clock in happening at the same time. The
reading of counter value may disrupt for transient state. If 8 bit counter is not
enough for counting, user can enable the interrupt and using the data RAM as
software counter for extending the counter stage.
CK0
Data Bus
Timer/Counter
M
U
X
CK1
CK2
CK3
PWMx Circuit
TCP2OV
Preload Data
TCP2S1
TCP2S0
TCP2L
Data Bus
TCP2EN
Figure: Timer/Counter/PWM
TCP1S1 TCP1S0 TCP1
PWM Output
PWM0,1,2
CK0
CK1
CK2
CK3
0
0
1
1
0
1
0
1
FS
TCP2
OSCH
TBCK
TB1OV
TCP2S1 TCP2S0 TCP2
CK0
CK1
CK2
CK3
0
0
1
1
0
1
0
1
FS
OSCH
TBCK
TCP1OV
FS: System scaled frequency.
TBCK: Peripheral clock source, 16KHZ in the RC mode. (Typical)
TB1OV: Time base 1st overflow output.
PWM0~2: TCP2 cycle time with PWMxD duty output signal
TCP1OV: Timer/counter1’s overflow output.
16’/04/06
Page 24 of 44
Ver.: 1.2
TTELEC [ TT Electronics ]
