TTP258
TonTouchTM
Preliminary
P-4: 8 bits Timer/Counter/PWM for TCP2
One 8-bit timer/counters (TCP2) with 4 kind clock sources and preload data
buffer can implement as a timer or counter feature. The clock sources of TCP2
are selected by TCP2S0 & TCP2S1 two bits of the timer control registers
(TCP2C). TCP2OV is the timer or counter overflow signal and the rising edge
will set the relative INT flag.
TCP2C[203H]: TCP2 Timer/counter/PWM control register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TCP2LD
R/W
Bit2
TCP2S1
R/W
Bit1
TCP2S0
R/W
Bit0
TCP2EN
R/W
TCP2EN: TCP2 counting enabled. (0: disable; 1: enable)
TCP2LD: TCP2 auto-reload enabled. (0: disable; 1: enable)
TCP2S1 & TCP2S0: TCP2 clock source selection bits.
TCP2S1
TCP2S0
Selected Clock source
0
0
1
1
0
1
0
1
CK0
CK1
CK2
CK3
TCP2L[204H]: TCP2 low nibble data register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
TCP2_3/TCP2D3 TCP2_2/TCP2D2 TCP2_1/TCP2D1 TCP2_0/TCP2D0
R/W
R/W
R/W
R/W
TCP2_3~TCP2_0: reading the counter low nibble data.
TCP2D3~TCP2D0: writing TCP2D low nibble of data buffer.
TCP2H[205H]: TCP2 low high data register[R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
TCP2_7/TCP2D7 TCP2_6/TCP2D6 TCP2_5/TCP2D5 TCP2_4/TCP2D4
R/W R/W R/W R/W
TCP2_7~TCP2_4: reading the counter high nibble data.
TCP2D7~TCP2D4: writing TCP2D high nibble of data buffer.
* TCP2D: Like a 8 bit TCP2 data register[R/W], default value [00H]
TCP2D
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit Name TCP2D7 TCP2D6 TCP2D5 TCP2D4 TCP2D3 TCP2D2 TCP2D1 TCP2D0
The special R/W function for TCP2 has different Target, AS writing TCP2H/L registers that are
updating preload data of the TCP2D. As read TCP2H/L registers that are the brand new TCP2
counter value.
16’/04/06
Page 22 of 44
Ver.: 1.2
TTELEC [ TT Electronics ]
