TTP258
TonTouchTM
Preliminary
S-11. Interrupts
The CPU provides only 1 interrupt vector ($001H) and no priority, but can
expand to multi-sources. Interrupt source includes external interrupts (INT0,
INT1), timer/counter interrupts (TCP1,TCP2), Time base timer interrupt
(TBxINT) or other peripheral device interrupt request (PERINT). The interrupt
control registers (INTC or INTC1) contain the interrupt control bits to enable
and disable corresponding interrupt request and the corresponding interrupt
request flags in the (INTF or INTF1) registers. Before finishing the INT service
routine, another INT request will keep waiting until program return from
interrupt routine.
If the interrupt request needs service, the programmer may set the
corresponding INT enable bit to allow interrupt active. External interrupts are
triggered by both falling and rising edge trigger and set the related interrupt
request flag (INTFx). The internal timer/counter interrupt is setting the TCPxF
to 1, resulting from the timer/counter overflow. The time base interrupt TBxINT
was provided 2 periodic interrupt request cycles for user operating a periodic
routine.
When the corresponding interrupt enable and flag bits is set to 1, the CPU
will active the interrupt service routine. Then CPU reads the service flag and
check the request priority then proceeds with the relative interrupt service.
After CPU writes the corresponding bits to 0 in the INTFx register, the service
flag will be cleared to 0(using STX #n, $m instruction). The INTF & INTF1
registers’ bit can only write “0” to clear the flag. User writes “1” to Flag bit with
no effect.
INT0 input type can select Schmitt or comparator by SPCON1 register, if
comparator select then the comparator reference voltage is the band gap
voltage(1.12+-10%), it will consumption more current than Schmitt because
band gap turn on. It can be used to detect VDD voltage for battery low and so
on.
16’/04/06
Page 17 of 44
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