TTP258
TonTouchTM
Preliminary
S-10. Special control register
SPCON0 [218H]: Special control register 0 [R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
CDSC2
R/W
Bit2
CDSC1
R/W
Bit1
CDSC0
R/W
Bit0
VREFS
R/W
VREFS: Voltage reference selection for touch sensor detect (0: 1/2 VDD; 1: 2/3 VDD), use in
TPNI select comparator output signal mode.
CDSC: Charge and discharge sequence control for touch sensor function
CDSC2 ~ CDSC0
Sequence change clock
000
001
010
011
100
101
110
111
OFF
8
12
16
24
32
Reserve
Reserve
SPCON1 [219H]: Special control register 1 [R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
INTTS
R/W
Bit2
Bit1
Bit0
-
-
-
-
-
-
INTTS: INT0 Interrupt input type selection (0: Schmitt; 1: comparator)
reference voltage use band gap voltage
Compare
The system oscillator generates the system control timing for CPU core
or peripheral devices with fixed control phase, so the waveform of
oscillator becomes sensitive to noise, abnormal duty especially fatal for
CPU. Any switching of clock source needs oscillation stable time (OST)
to make sure the oscillation is stable and synchronized with CPU timing
phase. The relative OST for different oscillator with reference value as
below table:
OST
From Stop state
oscillating
Unit
System clock(OSCH)
RC Peripheral clock(OSCL)
8
8
8
8
OSCH clock
OSCL RC clock
16’/04/06
Page 16 of 44
Ver.: 1.2
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