TTP258
TonTouchTM
Preliminary
S-8: RESET
The chip has four kinds of reset sources: POR (power on reset), External
reset, Watch dog timer reset, LVR (low voltage reset). The reset feature can be
divided into 2 kind groups that one is system reset and the other is CPU reset.
The system reset will initialize the CPU and peripheral device with default state.
The CPU reset only initializes the CPU state and keeps the peripheral state no
change.
.POR (power on reset)
The chip provides automatic reset function when the power is turned on. The
VDD should be below 1.6V and its rising slope (from 0.1VDD up to 0.9VDD)
needs less than 10ms.
.External Reset (RSTB)
This is one kind of system resetting signal, but only forced externally. When
the chip acknowledged the low level from the pin RSTB exceed 1 us, it will
generate the reset procedure to reset CPU & all the peripheral back to their
initial state (default values).
.Burn out Reset (Program sequence abnormal)
As CPU out of program area, the CPU can detect the abnormal condition and
generate a system reset request.
.Watch Dog Timer Reset
The reset signal will generate automatically when the watchdog timer runs
overflow. If the watchdog timer is cleared regularly by users’ program, no
watchdog reset will occur. Unless the MCU is forced into abnormal state, the
software-controlled procedure is disrupted and causing watchdog timer
overflow, then it will generate reset signal to initializes the chip returning to
normal operation.
.Low Voltage Reset (LVR)
The LVR function is used to monitor the supply voltage of MCU, it will
generate a reset signal (with 4*OSCL de-bounce time) to reset the
microcontroller as the VDD power falls below the default setting level VLVR. It
can also be enabled or disabled by programming “LVREN” bit in LVREN register
(304H). User write $5H to this register, it can enable LVREN, write $AH can
disable LVREN. If user writes other value to LVREN register, it cannot change
LVREN bit.
RESETF[300H]: reset source flag register[R/W], power on value [0000]
Register
Bit Name
Read/Write
Bit3
ROMF
R/W
Bit2
BOF
R/W
Bit1
LVRF
R/W
Bit0
WDTF
R/W
WDTF: Watch dog timer overflow reset flag (0: no active; 1: active)
LVRF: Low voltage reset flag (0: no active; 1: active)
BOF: Burn out flag (0: no active; 1: active)
ROMF: ROM fail flag (0: no active; 1: active)
(The RESETF is cleared by power on reset and external RESET)
16’/04/06
Page 14 of 44
Ver.: 1.2
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