TTP258
TonTouchTM
Preliminary
S-9. Power saving control register
PS[008H]: Power saving register[R/W] , default value [0100]
Register
Bit Name
Read/write
Bit3
Bit2
H/L
Bit1
Bit0
-
SLEEP
-
-
-
R/W
R/W
SLEEP: Into sleep mode. (0: inactive; 1: active)
H/L: System clock selection. (1: System clock; 0: peripheral clock)
The SLEEP bits will be cleared to “0” automatically, when the release
conditions occur from reset, interrupt, or input wake up.
PSP[009H]: Peripheral power saving register[R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
LDOEN
R/W
Bit2
Bit1
Bit0
-
-
-
-
-
-
LDOEN: LDO enable. (0: disable; 1: enable)
LVREN[304H]: LVR enable control register[R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LVREN
R/W
-
-
-
-
-
-
LVREN: low voltage reset enable, (0: disable, 1: enable), When write $5 to this address,
LVREN is set to 1 , write $A to this address, LVREN is clear to 0.
LDOFLAG[216H] : LDO falg register[R/W] , default value [0000]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LDOFAIL
R/W
-
-
-
-
-
-
LDOFAIL: When VDD voltage is small then LDO voltage, LDOFAIL will be set. This bit can be
clear by write 0.
16’/04/06
Page 15 of 44
Ver.: 1.2
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