TE
tmCH
T2316162A
Notes:
1. Enables on-chip refresh and address counters.
12. These parameters are referenced to
CAS
2. V (2.4V) and V (0.8V) are reference levels
IH IL
leading edge in EARLY WRITE cycles and
for measuring timing of input signals.
Transition times are measured between V
leading edge in LATE WRITE or READ-
WE
IH
MODIFY-WRITE cycles.
and V
.
(2.4V)
IL (0.8V)
13. During a READ cycle, if
is low then taken
OE
3. In addition to meet the transition rate
specification, all input signals must transit
HIGH before
goes high, I/O goes open,
CAS
if
is tied permanently low, a LATE
OE
between V and V in a monotonic manner.
IH
IL
WRITE or READ-MODIFY-WRITE operation
is not possible.
4. Assume that t
< t
(max). If t
RCD
is
RCD
RCD
greater than the maximum recommended value
shown in this table, t will increase by the
14. An initial pause of 100ms is required after
RAC
exceeds the value shown.
amount that t
power-up followed by eight
refresh
RAS
RCD
5. Assume that t
t
(max) .
≥
RCD RCD
cycles (
only or CBR) before proper
RAS
6. If
is low at the falling edge of
,
RAS
CAS
device operation is assured. The eight
RAS
cycle wake-ups should be repeated any time
the t refresh requirement is exceeded.
data-out will be maintained from the previous
cycle. To initiate a new cycle and clear the
REF
15.WRITE command is defined as
data-out buffer,
pulsed high.
7. Operation within the t
and
must be
CAS
RAS
going low.
WE
16. LATE WRITE and READ-MODIFY-WRITE
cycles must have both t and t met
(max) limit ensures
RCD
OFF2
OEH
that t
(max) can be met. t
(max) is
RCD
RAC
(
high during WRITE cycle) in order to
OE
specified as a reference point only; if t
greater than the specified t
access time is controlled by t
is
RCD
(max) limit,
CAC
limit ensures that
ensure that the output buffers will be open
during the WRITE cycles.
RCD
.
17. The I/Os open during READ cycles once
8. Operation within the t
RAD
t
or t
occur.
OFF1
OFF2
t
(max) can be met. t
(max) is
RAC RAD
18. The first
edge to transition low.
edge to transition high.
CAS
CAS
specified as a reference point only; if t is
RAD
(max) limit,
AA
must be satisfied for a
RRH
19. The last
greater than the specified t
access time is controlled by t
RAD
20. Output parameter (I/O) is referenced to
.
corresponding
and IO9~16 by
input, IO1~8 by
CASL
9. Either t
or t
CAS
RCH
READ cycle.
10. t (max) defines the time at which the
.
CASH
OFF1
output achieves the open circuit condition; it is
not a reference to V or V
21. Last falling
22. Last rising
edge to first rising
edge.
CAS
CAS
CAS
edge to next cycle's last rising
.
OH
AWD
OL
and
edge.
CAS
11. t
,
t
,
t
t
are
WCS
RWD
CWD
23. Last rising
edge to first falling
edge.
CAS
CAS
restrictive operating parameters in LATE
WRITE and READ-MODIFY-WRITE cycles
24. First IOs controlled by the first
to go low.
CAS
to go high.
only. If t
t
(min), the cycle is an
WCS
≥
WCS
25.Last IOs controlled by the last
CAS
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If t
26. Each
27. Last
must meet minimum pulse width.
to go low.
CAS
CAS
t
(min), t
RWD
≥
≥
RWD
(min) and t
AWD
(min), the
28. All IOs controlled, regardless
and
CASL
t
t
≥
AWD
CWD
CWD
.
CASH
29. Data outputs are measured with a load of 50pF.
The output reference levels are V /V
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
OH OL
=2.0V/0.8V; The input levels are V /V =
IH IL
of I/O (at access time and until
and
CAS
go back to V ) is indeterminate.
OE
3.0V/0V.
or
RAS
IH
taken low after
CAS
held high and
OE
WE
goes low result in a LATE WRITE(
controlled) cycle.
-
OE
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date:APR. 2002
Revision:E
TMT [ TAIWAN MEMORY TECHNOLOGY ]
