UCC28180
SLUSBQ5A –NOVEMBER 2013–REVISED NOVEMBER 2013
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Switching Element
The MOSFET/IGBT switch will be driven by a GATE output that is clamped at 15.2 V for VCC bias voltages
greater than 15.2 V. An external gate drive resistor is recommended to limit the rise time and to dampen any
ringing caused by the parasitic inductances and capacitances of the gate drive circuit; this will also help in
meeting any EMI requirements of the converter. The design example uses a 3.3-Ω resistor; the final value of any
design is dependent upon the parasitic elements associated with the layout of the design. To facilitate a fast turn
off, a standard 40-V, 1-A Schottky diode is placed anti-parallel with the gate drive resistor. A 10-kΩ resistor is
placed between the gate of the MOSFET/IGBT and ground to discharge the gate capacitance and protect from
inadvertent dv/dt triggered turn-on.
The conduction losses of the switch MOSFET, in this design are estimated using the RDS(on) at 125°C, found in
the device data sheet, and the calculated drain to source RMS current, IDS_RMS
:
PCOND = ID2S _ RMSRDS(on)125°C
(41)
(42)
RDS(on)125°C = 0.35W
POUT(max)
16V
IN_ RECTIFIED(min)
IDS _ RMS
=
2 -
V
3pVOUT
IN_ RECTIFIED(min)
(43)
360W
120 V
16 ´120 V
3p ´390 V
IDS _ RMS
=
2 -
= 3.639 A
(44)
(45)
PCOND = 3.639 A2 ´0.35W = 4.636W
The switching losses are estimated using the rise time, tr, and fall time, tf, of the MOSFET gate, and the output
capacitance losses.
tr = 5ns
tf = 4.5ns
COSS = 780pF
(46)
(tr + tf ) + 0.5COSSV2
OUT û
é
ù
PSW = fSW 0.5VOUT IN(max)
I
ë
(47)
(48)
é
ë
2 ù
û
PSW = 118kHz 0.5 ´390 V ´ 6.436A(5ns + 4.5ns) + 0.5´ 780pF´390 V = 8.407W
Total FET losses
PCOND + PSW = 4.636W + 8.407W = 13.042W
(49)
The MOSFET requires an appropriately sized heat sink.
28
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