UCC27423, UCC27424, UCC27425
SLUS545D –NOVEMBER 2002–REVISED MAY 2013
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There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by the following:
1
2
2
P + 2 CV f
, where f is the switching frequency.
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD = 12V, CLOAD = 10nF, and f = 300kHz, the power loss can be calculated as:
P = 10nF × (12)2 × (300kHz) = 0.432W
With a 12V supply, this would equate to a current of:
0.432 W
12 V
P
V
I +
+
+ 0.036 A
(1)
The actual current measured from the supply was 0.037A, and is very close to the predicted value. But, the IDD
current that is due to the IC internal consumption should be considered. With no load the IC current draw is
0.0027A. Under this condition the output rise and fall times are faster than with a load. This could lead to an
almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,
these small current differences are buried in the high frequency switching spikes, and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10nF load is reasonably close to that
expected.
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for
power:
2
P + C V f + Q f
g
(2)
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage.
ENABLE
UCC27423/4/5 provides dual Enable inputs for improved control of each driver channel operation. The inputs
incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100kΩ resistor
for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when ENBA and
ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver and therefore
can be left open for standard operation. However, if the enable pin is left open, it is recommended to terminate
any PCB traces to be as short as possible to limit noise. If large noise is present due to non-optimal PCB layout,
it is recommended to tie the Enable pin to Vcc or to add a filter capacitor (0.1 µF) to the Enable pin. The output
states when the drivers are disabled is low regardless of the input state. See the truth table of Table 1 for the
operation using enable logic.
Enable input are compatible with both logic signals and slow changing analog signals. They can be directly
driven or a power-up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and
ENBB control input A and input B respectively.
10
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