TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
Table 3-34. Fast-Switch Overlay Delay
Subaddress 29h
Default
17h
7
6
5
4
3
2
1
0
Reserved
FSO delay [4:0]
Overlay delay [4:0]: Adjusts delay between digital RGB and FSO
11111 = 8 pixel delay
⋮
11000 = 1 pixel delay
10111 = 0 delay (default)
10110 = –1 pixel delay
⋮
00000 = –23 pixel delay
When SCART mode is active (RGB component) the recommended setting for this register is 1Bh; otherwise, 17h is recommended.
Table 3-35. Fast-Switch SCART Delay
Subaddress 2Ah
Default
1Ch
7
6
5
4
3
2
1
0
Reserved
FSS delay [4:0]
FSS delay [4:0]: Adjusts delay between FSS and component RGB
11111 = 3 pixel delay
⋮
11101 = 1 pixel delay
11100 = 0 delay (default)
11011 = –1 pixel delay
⋮
00000 = –23 pixel delay
Table 3-36. Overlay Delay
Subaddress 2Bh
Default 12h
7
6
5
4
3
2
1
0
Reserved
Overlay delay [4:0]
Overlay delay[4:0]: Adjusts delay between digital RGB and component video
11111 = 13 pixel delay
⋮
10011 = 1 pixel delay
10010 = 0 delay (default)
10001 = –1 pixel delay
⋮
00000 = –18 pixel delay
When SCART mode is active (RGB component) the recommended setting for this register is 16h; otherwise, 12h is recommended.
Copyright © 2005–2011, Texas Instruments Incorporated
Internal Control Registers
55
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