TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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Table 3-32. Embedded Sync Offset Control 2
Subaddress 27h
Default 00h
7
6
5
4
3
2
1
0
Offset [7:0]
This register allows the line relationship between the embedded F bit and V bit signals to be offset from the 656 standard positions, and
moves F relative to V. This register is only applicable to input video signals with standard number of lines.
0111 1111 = 127 lines
⋮
0000 0001 = 1 line
0000 0000 = 0 line
1111 1111 = –1 line
⋮
1000 0000 = –128 lines
Table 3-33. Fast-Switch Control
Subaddress 28h
Default
C0h
7
6
5
4
3
2
1
0
Mode [2:0]
Reserved
Polarity FSO
Polarity FSS
Mode [2:0]:
000 = CVBS ↔ SCART
001 = CVBS, S_VIDEO ↔ Digital overlay
010 = Component ↔ Digital overlay
011 = (CVBS ↔ SCART) ↔ Digital overlay
100 = (CVBS ↔ Digital overlay) ↔ SCART
101 = CVBS ↔ (SCART ↔ Digital overlay)
110 = Composite (default)
111 = Component
Polarity FSO:
0 = If FSO = 0, then output = YPbPr
If FSO = 1, then output = Digital RGB (default)
1 = If FSO = 0, then output = Digital RGB
If FSO = 1, then output = YPbPr
Polarity FSS:
0 = If FSO = 0, then output = RGB
If FSO = 1, then output = CVBS (4A) (default)
1 = If FSO = 0, then output = CVBS (4A)
If FSO = 1, then output = RGB
See TI application note SLEA016, TVP5146 SCART and OSD, for more information on SCART overlay and digital overlay programming.
54
Internal Control Registers
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