TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
Table 3-28. VS Stop Line
Subaddress 20h–21h
Default
004h/001h
Subaddress
20h
7
6
5
4
3
2
1
0
VS stop [7:0]
21h
Reserved
VS stop [9:8]
VS stop [9:0]: This is an absolute line number.
The TVP5160 decoder updates the VS stop only when the VS stop MSB byte is written to. If these registers are modified, then the
TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must be
set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-29. VBLK Start Line
Subaddress 22h–23h
Default
001h/26Fh
Subaddress
22h
7
6
5
4
3
2
1
0
VBLK start [7:0]
23h
Reserved
VBLK start [9:8]
VBLK start [9:0]: This is an absolute line number.
The TVP5160 decoder updates the VBLK start line only when the VBLK start MSB byte is written to. If these registers are modified, then
the TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must
be set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-30. VBLK Stop Line
Subaddress 24h–25h
Default
001h/26Fh
Subaddress
24h
7
6
5
4
3
2
1
0
VBLK stop [7:0]
25h
Reserved
VBLK stop [9:8]
VBLK stop [9:0]: This is an absolute line number.
The TVP5160 decoder updates the VBLK stop only when the VBLK stop MSB byte is written to. If these registers are modified, then the
TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must be
set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-31. Embedded Sync Offset Control 1
Subaddress 26h
Default
00h
7
6
5
4
3
2
1
0
Offset [7:0]
This register allows the line position of the embedded F bit and V bit signals to be offset from the 656 standard positions. This register is
only applicable to input video signals with standard number of lines.
0111 1111 = 127 lines
⋮
0000 0001 = 1 line
0000 0000 = 0 line
1111 1111 = –1 line
⋮
1000 0000 = –128 lines
Copyright © 2005–2011, Texas Instruments Incorporated
Internal Control Registers
53
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