TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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List of Figures
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TVP5160 PNP-Package Terminal Diagram .................................................................................. 15
Analog Processors and A/D Converters ...................................................................................... 18
Luminance Edge-Enhancer Peaking Block ................................................................................... 21
Peaking Filter Frequency Response NTSC/PAL ITU_R BT.601 Sampling............................................... 21
Reference Clock Configuration ................................................................................................. 22
RTC Timing ....................................................................................................................... 23
Fast-Switches for SCART and Digital Overlay ............................................................................... 25
Vertical Synchronization Signals for 525-Line System ...................................................................... 28
Vertical Synchronization Signals for 625-Line System ...................................................................... 28
Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode.................................................................. 29
Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode.................................................................. 30
VS Position With Respect to HS for Interlaced Signals ..................................................................... 31
VS Position With Respect to HS for Progressive Signals................................................................... 31
VBUS Access ..................................................................................................................... 33
Reset Timing...................................................................................................................... 37
Teletext Filter Function .......................................................................................................... 80
Application Example ............................................................................................................. 95
Clocks, Video Data, and Sync Timing ....................................................................................... 100
I2C Host Port Timing............................................................................................................ 100
SDRAM Interface Timing ...................................................................................................... 101
TVP5160 Timing Relationship with K4S161622E-80 SDRAM............................................................ 102
128-Pin PowerPAD Package.................................................................................................. 105
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List of Figures
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