TSC2007-Q1
SBAS545 –SEPTEMBER 2011
www.ti.com
TIMING INFORMATION
SDA
tSU, STA
tSU, DAT
tBUF
tHD, STA
tHD, DAT
tLOW
tSU, STO
SCL
tHD, STA
tHIGH
tR
tF
START
CONDITION
REPEATED
START
STOP
START
CONDITION
CONDITION
CONDITION
Figure 1. Detailed I/O Timing
TIMING REQUIREMENTS: I2C Standard Mode (SCL = 100kHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE STANDARD MODE PARAMETERS
TEST CONDITIONS
MIN
0
TYP
MAX UNIT
SCL clock frequency
fSCL
100 kHz
Bus free time between a STOP and START condition
Hold time (repeated) START condition
Low period of SCL clock
tBUF
4.7
4.0
4.7
4.0
4.7
0
μs
μs
μs
μs
μs
tHD, STA
tLOW
tHIGH
tSU, STA
tHD, DAT
tSU, DAT
tR
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
3.45
μs
ns
Data setup time
250
Rise time for both SDA and SCL signals (receiving)
Fall time for both SDA and SCL signals (receiving)
Fall time for both SDA and SCL signals (transmitting)
Setup time for STOP condition
Cb = total bus capacitance
Cb = total bus capacitance
Cb = total bus capacitance
1000
300
ns
tF
ns
tF
250
ns
tSU, STO
Cb
4.0
μs
Capacitive load for each bus line
Cb = total capacitance of one bus line in pF
40 SCL + 127 CCLK, VDD = 1.8V
49 SCL + 148 CCLK, VDD = 1.8V
VDD = 1.8V
400
pF
8 bits
434.7
570.9
2.3
μs
Cycle time
12 bits
μs
8 bits
kSPS
kSPS
kHz
kHz
Effective throughput
12 bits
VDD = 1.8V
1.75
16.1
12.26
8 bits
Equivalent rate = effective throughput × 7
12 bits
VDD = 1.8V
VDD = 1.8V
6
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TSC2007-Q1
TI [ TEXAS INSTRUMENTS ]
