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TSC2007IPWRQ1 参数 Datasheet PDF下载

TSC2007IPWRQ1图片预览
型号: TSC2007IPWRQ1
PDF下载: 下载PDF文件 查看货源
内容描述: 1.2V至3.6V , 12位,纳安级,4线微型触摸屏控制器I2Câ ?? ¢接口 [1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Micro TOUCH SCREEN CONTROLLER with I2C™ Interface]
分类和应用: 消费电路商用集成电路光电二极管控制器
文件页数/大小: 39 页 / 787 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TSC2007-Q1  
SBAS545 SEPTEMBER 2011  
www.ti.com  
TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 3.4MHz)  
All specifications typical at 40°C to +85°C, VDD = 1.6V, unless otherwise noted.  
2-WIRE HIGH-SPEED MODE PARAMETERS  
TEST CONDITIONS  
MIN  
0
TYP MAX UNIT  
SCL clock frequency  
fSCL  
3.4 MHz  
Hold time (repeated) START condition  
Low period of SCL clock  
tHD, STA  
tLOW  
tHIGH  
tSU, STA  
tHD, DAT  
tSU, DAT  
tR  
160  
160  
60  
ns  
ns  
ns  
ns  
High period of the SCL clock  
Setup time for a repeated START condition  
Data hold time  
160  
0
70  
ns  
ns  
Data setup time  
10  
Rise time for SCL signal (receiving)  
Rise time for SDA signal (receiving)  
Fall time for SCL signal (receiving)  
Fall time for SDA signal (receiving)  
Fall time for both SDA and SCL signals (transmitting)  
Setup time for STOP condition  
Capacitive load for each bus line  
Cb = total bus capacitance  
Cb = total bus capacitance  
Cb = total bus capacitance  
Cb = total bus capacitance  
Cb = total bus capacitance  
10  
40  
80  
40  
80  
80  
ns  
tR  
10  
ns  
tF  
10  
ns  
tF  
10  
ns  
tF  
10  
ns  
tSU, STO  
Cb  
160  
ns  
Cb = total capacitance of one bus line in pF  
40 SCL + 127 CCLK, VDD = 1.8V  
49 SCL + 148 CCLK, VDD = 1.8V  
VDD = 1.8V  
100  
pF  
8 bits  
46.5  
95.3  
μs  
Cycle time  
12 bits  
μs  
8 bits  
21.52  
10.49  
150.65  
73.46  
kSPS  
kSPS  
kHz  
kHz  
Effective throughput  
12 bits  
VDD = 1.8V  
8 bits  
Equivalent rate = effective throughput × 7  
12 bits  
VDD = 1.8V  
VDD = 1.8V  
8
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Copyright © 2011, Texas Instruments Incorporated  
Product Folder Link(s): TSC2007-Q1  
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