TSC2007-Q1
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SBAS545 –SEPTEMBER 2011
THROUGHPUT RATE AND I2C BUS TRAFFIC
Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is
much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The
throughput is further limited by the I2C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bit
resolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I2C bandwidth for the
system to use on other devices.
Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal
4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency
reduces to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate.
12-Bit Operation
For 12-bit operation, sending the conversion result across the I2C bus takes 49 bus clocks (SCL clock). Each
write cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle
takes 29 I2C cycles (START, STOP, address byte,
3 ACKs, and data bytes 1 and 2). Seven
sample-and-conversions take 19 x 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks.
For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 5. Because the first
acquisition cycle overlaps with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For
12-bit mode, (19 × 7 + 19) – 4 = 148 CCLKs plus I/O are required.
8-Bit Operation
For 8-bit operation, sending the conversion result across the I2C bus takes 40 bus clocks (SCL clock). Each write
cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 20
I2C cycles (START, STOP, address byte, 2 ACKs, and data byte 1). Seven sample-and-conversions takes 16 x 7
internal clocks to complete. The MAV filter loop requires 19 internal clocks. For VDD = 1.2V, the complete
processed data cycle time calculations are shown in Table 5. Because the first acquisition cycle overlaps with the
I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 8-bit mode, (16 × 7 + 19) – 4 = 127
CCLKs plus I/O are required.
Table 5. Measurement Cycle Time Calculations
STANDARD MODE: 100kHz (Period = 10μs)
8-Bit
40 × 10μs + 127 × 313ns = 439.8μs (2.27kSPS through the I2C bus)
49 × 10μs + 148 × 625ns = 582.5μs (1.72kSPS through the I2C bus)
12-Bit
FAST MODE: 400kHz (Period = 2.5μs)
8-Bit
40 × 2.5μs + 127 × 313ns = 139.8μs (7.15kSPS through the I2C bus)
49 × 2.5μs + 148 × 625ns = 215μs (4.65kSPS through the I2C bus)
12-Bit
HIGH-SPEED MODE: 1.7MHz (Period = 588ns)
8-Bit
40 × 588ns + 127 × 313ns = 63.3μs (15.79kSPS through the I2C bus)
49 × 588ns + 148 × 625ns = 121.3μs (8.24kSPS through the I2C bus)
12-Bit
HIGH-SPEED MODE: 3.4MHz (Period = 294ns)
8-Bit
40 × 294ns + 127 × 313ns = 51.6μs (19.39kSPS through the I2C bus)
49 × 294ns + 148 × 625ns = 106.9μs (9.35kSPS through the I2C bus)
12-Bit
As an example, use VDD = 1.2V and 12-bit mode with the Fast-mode I2C clock (fSCL = 400kHz). The equivalent
TSC throughput is at least seven times faster than the effective throughput across the bus (4.65k x 7 =
32.55kSPS). The supply current to the TSC for this rate and configuration is 128μA. To achieve an equivalent
sample throughput of 8.2kSPS using the device without preprocessing, the TSC2007-Q1 consumes only
(8.2/32.55) × 128μA = 32.24μA.
Copyright © 2011, Texas Instruments Incorporated
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