TSC2007-Q1
SBAS545 –SEPTEMBER 2011
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POWER-ON RESET (POR)
During TSC2007-Q1 power-up, an internal power-on reset (POR) is automatically implemented. The POR brings
the TSC to the default working condition, and checks the A0 and A1 pins for the two LSBs of the I2C address.
The TSC2007-Q1 senses the power-up curve to decide whether or not to implement a POR.
It is required to follow the power-on/off slope and interval requirements, as provided in the Electrical
Characteristics
, in order to ensure a proper POR of the TSC2007-Q1.
tVDD_OFF_RAMP
tVDD_ON_RAMP
1.2V to 3.6V
0.9V
VDD
0.3V
0V
tVDD_OFF
Figure 35. Power-On Reset Timing
Table 7. Timing Requirements for Figure 35
PARAMETER
TEST CONDITIONS
TA = –40°C to +85°C
MIN
2
MAX UNIT
VDD off ramp
kV/s
s
TA = –40°C to +85°C, VDD = 0V
TA = –20°C to +85°C, VDD = 0V
TA = –40°C to +85°C
1.2
0.3
12
VDD off time
VDD on ramp
s
kV/s
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Recommended VDD Off Time
for TA = -40°C to +85°C
Typical VDD Off Time for Various Temperatures
-40
-20
0
20
40
60
80
100
Temperature (°C)
Figure 36. VDD Off Time vs Temperature
32
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