TSC2007-Q1
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SBAS545 –SEPTEMBER 2011
START A CONVERTER FUNCTION/WRITE CYCLE
A conversion/write cycle begins when the master issues the address byte containing the slave address of the
TSC2007-Q1, with the eighth bit equal to a 0 (R/W = 0), as shown in Table 1. Once the eighth bit has been
received, and the address matches the A1-A0 address input pin setting, the TSC2007-Q1 issues an
acknowledge.
When the master receives the acknowledge bit from the TSC2007-Q1, the master writes the command byte to
the slave (see Table 2). After the command byte is received by the slave, the slave issues another acknowledge
bit. The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in
Figure 31.
SCL
Address Byte
Command Byte
R/W
0
1
0
0
1
0
A1 A0
0
0
C3 C2 C1 C0 PD1 PD0
M
X
SDA
TSC2007
ACK
TSC2007
ACK
Acquisition
Conversion
START
STOP or
Repeated START
Figure 31. Complete I2C Serial Write Transmission
If the master sends additional command bytes after the initial byte, but before sending a STOP or repeated
START condition, the TSC2007-Q1 does not acknowledge those bytes.
The input multiplexer channel for the A/D converter is selected when bits C3 through C0 are clocked in. If the
selected channel is an X-,Y-, or Z-position measurement, the appropriate drivers turn on once the acquisition
period begins.
When R/W = 0, the input sample acquisition period starts on the falling edge of SCL when the C0 bit of the
command byte has been latched, and ends when a STOP or repeated START condition has been issued. A/D
conversion starts immediately after the acquisition period. The multiplexer inputs to the A/D converter are
disabled once the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respective
touch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 31.
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