TSC2007-Q1
SBAS545 –SEPTEMBER 2011
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I2C High-Speed Mode (Hs Mode)
The TSC2007-Q1 can operate with high-speed I2C masters. To do so, the pull-up resistor on SCL must be
changed to an active pull-up, as recommended in the I2C specification.
Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus
specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:
1. START condition (S)
2. 8-bit master code (00001xxx)
3. Not-acknowledge bit (N)
Figure 30 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for
triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code
indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the
Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is
followed by a not-acknowledge bit (N).
After the not-acknowledge bit (N) and SCL have been pulled-up to a HIGH level, the master switches to
Hs-mode and enables the current-source pull-up circuit for SCL (at time tH shown in Figure 30). Because other
devices can delay the serial transfer before tH by stretching the LOW period of SCL, the master enables the
current-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus
speeding up the last part of the rise time of the SCL.
The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit
address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition
and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up
circuit. This disabling enables other devices, such as the TSC2007-Q1, to delay the serial transfer (until the
converted data are stored in the TSC internal shift register) by stretching the LOW period of SCL. The master
re-enables its current-source pull-up circuit again when all devices have released SCL, and SCL reaches a HIGH
level, which speeds up the last part of the SCL signal rise time.
Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode
after a STOP condition (P). To reduce the overhead of the master code, it is possible for the master to link a
number of Hs mode transfers, separated by repeated START conditions (Sr).
8-Bit Master Code 00001xxx
N
tH
S
SDA
SCL
1
2 to 5
6
7
8
9
Fast or Standard Mode
R/W
A
n x (8-Bit DATA
+
A/N)
7-Bit Slave Address
Sr
Sr P
SDA
SCL
1
2 to 5
6
7
8
9
1
2 to 5
6
7
8
9
If P then
Fast or Standard Mode
High-Speed Mode
If Sr (dotted lines)
then High-Speed Mode
A = Acknowledge (SDA LOW)
= Current Source Pull-Up
= Resistor Pull-Up
tH
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
tFS
Sr = Repeated START Condition
Figure 30. Complete High-Speed Mode Transfer
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