TSC2007-Q1
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SBAS545 –SEPTEMBER 2011
Figure 29 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two
types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave
address and each received byte.
2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is
transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are
transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other
than the last byte. At the end of the last received byte, a not-acknowledge is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends
with a STOP condition or a repeated START condition. Because a repeated START condition is also the
beginning of the next serial transfer, the bus is not released.
The TSC2007-Q1 may operate in the following two modes:
1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit.
2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver
mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data are
transmitted on SDA by the TSC2007-Q1 while the serial clock is input on SCL. START and STOP conditions
are recognized as the beginning and end of a serial transfer.
I2C Fast or Standard Mode (F/S Mode)
In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information
section.
In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a
START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has
finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high, as shown in Figure 29. The bus is free for another transmission after a STOP
condition has occurred. Figure 29 shows the complete F/S mode transfer on the I2C, 2-wire serial interface. The
address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA
state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are
transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word
plus acknowledge bit).
SDA
MSB
Slave Address
R/W
Direction Bit
Acknowledgement
Signal from Receiver
Acknowledgement
Signal from Receiver
1
2
6
7
8
9
1
2
3-8
8
9
SCL
ACK
ACK
START
Condition
STOP Condition
or Repeated
START Condition
Repeated If More Bytes Are Transferred
Figure 29. Complete Fast- or Standard-Mode Transfer
Copyright © 2011, Texas Instruments Incorporated
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