TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N –MARCH 2010–REVISED APRIL 2012
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VDD1 and VDD2 Voltage Control Through SCLSR_EN1 and SDASR_EN2 Signals
Figure 10 shows the VDD1 and VDD2 voltage control through the SCLSR_EN1 and SDASR_EN2 signals timing
characteristics.
SCLSR_EN2
tdDVSEN
tdDVSENL
tdDVSEN
tdDVSENL
1.2 V
0.8 V
VDD1/VFB1
SW1
TSTEP[2:0]=001
TSTEP[2:0]=011
PFM (pulse skipping) mode
PFM (pulse
skipping) mode
PFM (pulse
skipping) mode
SWCS046-021
PWM mode
PWM mode
NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG
Figure 10. VDD1 Supply Voltage Control Though SCLSR_EN1
Table 9. VDD1 Supply Voltage Control Through SCLSR_EN1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
tdDVSEN: SCLSR_EN1 or SCLSR_EN2 edge to
VDD1 or VDD2 voltage change delay
2 × tCK32k = 62
tdDVSENL: VDD1 or VDD2 voltage settling delay
TSTEP[2:0] = 001
32
0.4/7.5 = 53
160
µs
TSTEP[2:0] = 011 (default)
TSTEP[2:0] = 111
SMPS Switching Synchronization
Figure 11 shows the SMPS switching synchronization timing characteristics.
SWIO
tdswio2sw1
tdviosync
SW1
SW2
tdswio2sw2
tdswio2sw3
SW3
SWCS046-025
NOTE: VDD1 or VDD2 switching synchronization is available in PWM mode (VDD1_PSKIP = 0 or VDD2_PSKIP = 0). SMPS
external clock (GPIO_CKSYNC) synchronization is available when VIO PWM mode is set (VIO_PSKIP = 0).
Figure 11. SMPS Switching Synchronization
Table 10. SMPS Switching Synchronization Timing Characteristics
PARAMETER
TEST CONDITIONS
VDD1_PSKIP = 0,
MIN
TYP
MAX
UNIT
tdSWIO2SW1: delay from SWIO rising edge to SW1
rising edge
DCDCCKSYNC[1:0] = 11
DCDCCKSYNC[1:0] = 01
VDD2_PSKIP = 0,
160
220
ns
tdSWIO2SW2: delay from SWIO rising edge to SW1
rising edge
DCDCCKSYNC[1:0] = 11
DCDCCKSYNC[1:0] = 01
160
290
ns
36
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