TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N –MARCH 2010–REVISED APRIL 2012
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Device SLEEP State Control
Figure 7 shows the device SLEEP state control timing characteristics.
tACT2SLP
tSLP2ACT
SLEEP
VIO/VFBIO
1.8 V
PWM mode
1.8 V
Low-power mode
1.8 V
PWM mode
SWIO
1.8 V
Active mode
1.8 V
Low-power mode
1.8 V
Active mode
VAUX1
3.3 V
Pulse skip mode
3.3 V
Pulse skip mode
3.3 V
Low-power mode
VDD2/VFB2
SW2
tdONDCDCSLP
1.2 V
PWM mode
1.2 V
PWM mode
Off
VDD1/VFB1
SW1
1.8 V
Active mode
Off
Off
1.8 V
Active mode
VPLL
1.8 V
Active mode
1.8 V
Active mode
VDAC
1.8 V
Active mode
1.8 V
Active mode
1.8 V
Active mode
VAUX2
VMMC
3.3 V
Active mode
3.3 V
Active mode
3.3 V
Low-power mode
tSLP2ACTCK32K
CLK32KOUT
tACT2SLPCK32K
tdSLPONST
tdSLPON1
tdSLPONST
SWCS046-024
NOTE: Registers programming: VIO_PSKIP
=
0, VDD1_PSKIP
=
0, VDD1_SETOFF
=
1, VDAC_SETOFF
=
1,
VPLL_SETOFF = 1, VAUX2_KEEPON = 1
Figure 7. Device SLEEP State Control
Table 7. Device SLEEP State Control Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SLEEP falling edge to supply in low power
mode
(SLEEP resynchronization delay)
2 × tCK32k
62
=
=
3 × tCK32k
94
=
tACT2SLP
µs
tACT2SLP + 3 ×
tCK32k
tACT2SLP
tSLP2ACT
tSLP2ACTCK32K
tdSLPON1
SLEEP falling edge to CLK32KOUT low
156
188
µs
µs
µs
µs
SLEEP rising edge to supply in high power
mode
8 × tCK32k
250
9 × tCK32k
281
=
tSLP2ACT + 3 ×
tCK32k
SLEEP rising edge to CLK32KOUT running
344
281
375
312
SLEEP rising edge to time step 1 of the tun-on
sequence from SLEEP state
tSLP2ACT + 1 ×
tCK32k
turn-on sequence step duration, from SLEEP
state
TSLOT_LENGTH[1:0] = 00
TSLOT_LENGTH[1:0] = 01
TSLOT_LENGTH[1:0] = 10
TSLOT_LENGTH[1:0] = 11
0
tdSLPONST
µs
us
200
500
2000
VDD1, VDD2 or VIO tun-on delay from tun-on
sequence time step
2 × tCK32k
62
=
tdSLPONDCDC
34
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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