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SLVS818 – APRIL 2008
RECOMMENDED OPERATING CONDITIONS
MIN
V
I
T
J
Input voltage
Operating virtual-junction temperature
(2)
MAX
6
125
UNIT
V
°C
3
–55
PACKAGE DISSIPATION RATINGS
(1)
PACKAGE
20-Pin PWP with solder
20-Pin PWP without solder
(1)
(2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
26°C/W
57.5°C/W
T
A
= 25°C
POWER RATING
3.85 W
(3)
1.73 W
T
A
= 70°C
POWER RATING
2.12 W
0.96 W
T
A
= 85°C
POWER RATING
1.54 W
0.69 W
(3)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
a. 3 inch
×
3 inch, 2 layers, Thickness: 0.062 inch
b. 1.5 oz copper traces located on the top of the PCB
c. 1.5 oz copper ground plane on the bottom of the PCB
d. Ten thermal vias (see recommended land pattern in application section of this data sheet)
Maximum power dissipation may be limited by overcurrent protection.
ELECTRICAL CHARACTERISTICS
T
J
= –55°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE, VIN
VIN input voltage range
f
s
= 350 kHz, SYNC = 0.8 V, RT open
Quiescent current
f
s
= 550 kHz, SYNC
≥
2.5 V, RT open, phase pin open
Shutdown, SS/ENA = 0 V
UNDERVOLTAGE LOCKOUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
Rising and falling edge deglitch, UVLO
BIAS VOLTAGE
V
O
Output voltage, VBIAS
Output current, VBIAS
(2)
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3
6.2
8.4
1
6
9.6
12.8
1.4
V
mA
2.95
2.70
0.10
2.80
0.16
2.5
3
V
V
µs
I
(VBIAS)
= 0
2.70
2.80
2.95
100
V
µA
CUMULATIVE REFERENCE
V
ref
Accuracy
0.880
0.891
0.900
V
REGULATION
Line regulation
(1)
Load regulation
(1)
(3)
I
L
= 1.5 A, f
s
= 350 kHz, T
J
= 85°C
I
L
= 1.5 A, f
s
= 550 kHz, T
J
= 85°C
I
L
= 0 A to 3 A, f
s
= 350 kHz, T
J
= 85°C
I
L
= 0 A to 3 A, f
s
= 550 kHz, T
J
= 85°C
0.07
0.07
0.03
0.03
%/V
(3)
%/A
(1)
(2)
(3)
Specified by design
Static resistive loads only
Specified by the circuit used in
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