TPS54383, TPS54386
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SLUS774B–AUGUST 2007–REVISED OCTOBER 2007
Skipping
SW Waveform
SW Waveform
V
= 12 V
IN
V
= 5 V
OUT
V
OUT
Ripple
V
OUT
Ripple
Inductor
Current
Steady State
IN = 12 V
VOUT = 5 V
Inductor
Current
V
Figure 32. Steady State
Figure 33. Skipping
DESIGN HINT
If additional output capacitance is required to reduce the output voltage ripple during
DCM operation, be sure to recheck Feedback Loop and Inductor-Capacitor (L-C)
Filter Selection and Maximum Output Capacitance sections.
SW Node Ringing
A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to
decrease the voltage waveform ringing at the SW node to less than 5 volts peak and of a duration of less than
30-ns. In addition to following good printed circuit board (PCB) layout practices, there are a couple of design
techniques for reducing ringing and noise.
SW Node Snubber
Voltage ringing observable at the SW node is caused by fast switching edges and parasitic inductance and
capacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, an
R-C snubber may be used to dampen the ringing and ensure proper operation over the full load range.
DESIGN HINT
A series-connected R-C snubber (C = between 330 pF and 1 nF, R = 10 Ω)
connected from SW to GND reduces the ringing on the SW node.
Bootstrap Resistor
A small resistor in series with the bootstrap capacitor reduces the turn-on time of the internal MOSFET, thereby
reducing the rising edge ringing of the SW node.
DESIGN HINT
A resistor with a value between 1Ω and 3Ω may be placed in series with the bootstrap
capacitor to reduce ringing on the SW node.
DESIGN HINT
Placeholders for these components should be placed on the initial prototype PCBs in
case they are needed.
Copyright © 2007, Texas Instruments Incorporated
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