TPS386000-Q1
SBVS149 –SEPTEMBER 2010
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Table 3. SVS-3 Truth Table
OUTPUT
CONDITION
SENSE3 < VITN
SENSE3 > VITN
TPS386000-Q1
RESET3 = Low
RESET3 = High
STATUS
Reset asserted
Reset released after delay
Table 4. SVS-4 Truth Table
OUTPUT
CONDITION
TPS386000-Q1
RESET4 = Low
RESET4 = Low
RESET4 = Low
RESET4 = High
STATUS
Reset asserted
SENSE4L < VITN
SENSE4L < VITN
SENSE4L > VITN
SENSE4L > VITN
SENSE4H > VITP
SENSE4H < VITP
SENSE4H > VITP
SENSE4H < VITP
Reset asserted
Reset asserted
Reset released after delay
Table 5. Watchdog Timer (WDT) Truth Table
CONDITION
OUTPUT
RESET1 OR
RESET1
TPS386000-Q1
STATUS
WDO
WDO
WDI PULSE INPUT
Remains in WDT
Low
Low
Low
Low
High
Asserted
Toggling
WDO = low
timeout
Remains in WDT
High
High
High
Asserted
Released
Released
610ms after last WDI↑ or WDI↓
Toggling
WDO = low
timeout
Remains in WDT
WDO = low
timeout
Remains in WDT
610ms after last WDI↑ or WDI↓
WDO = low
timeout
High
High
High
Low
Low
Low
Asserted
Asserted
Released
Toggling
610ms after last WDI↑ or WDI↓
Toggling
WDO = high
WDO = high
WDO = high
Normal operation
Normal operation
Normal operation
Enters WDT
timeout
High
Low
Released
610ms after last WDI↑ or WDI↓
WDO = low
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