TPS23750
TPS23770
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SLVS590A–JULY 2005–REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
Bias Supplies
The TPS23750 has two bias supplies, the AUX input/output and the VBIAS supply, each with its own UVLO.
The AUX supply is a current-limited, 10 V regulator that draws its current from VDD. It may be overridden by
feeding a higher external voltage into this pin to improve efficiency. The gate driver draws large current pulses
from this rail. It requires low-impedance bypass capacitors, such as a 1 µF ceramic capacitor, located next to the
TPS23750 and connected by low-impedance connections. A UVLO prevents gate drive if the voltage is less than
8 V. A 17.5 V overvoltage lockout (OVLO) on AUX prevents an open-loop converter, such as the one in Figure 1,
from damaging the part by inhibiting gate drive. The VBIAS regulator draws its power from the AUX pin.
The VBIAS regulator is a current-limited, 5.1 V regulator that requires a capacitor between 0.08 µF–1.5 µF from its
output to RTN. An optocoupler can be powered from this rail. Current drawn from the VBIAS pin should not
exceed 5 mA. This regulator also has a UVLO that turns the converter off if it is pulled below 4.6 V.
BLANKING CONSIDERATIONS AND RSP
Programmable blanking typically eliminates the need for the traditional RC filter on the RSP input. Blanking
prevents the current-mode and current-limit comparators from reacting to the current spike that occurs as the
converter’s switching MOSFET turns on. This current spike consists of the MOSFET gate current, parasitic drain
capacitance current, and output rectifier recovery current. The required blanking period is highly dependent on
the specific design. Having too short a blanking time causes the converter to current limit, or switch erratically at
less than full load. A longer blanking time increases the minimum load required before cycle skipping occurs. The
power required to run an Ethernet link should provide most PDs adequate load to prevent cycle skipping.
Starting recommendations for the BL setting are:
•
•
•
Use the long blanking period for transformer-based designs operating below about 150 kHz or using
synchronous rectifiers.
Use the short blanking period for transformer-based designs operating above 150 kHz or using Schottky
output diodes.
Use the short blanking period for buck or boost converter topologies.
BL pin connections to achieve each blanking length are listed below.
BL CONNECTION
BLANKING OPERATION
Open
RSN
VBIAS
None (Minimum current-sense loop delay)
Minimum plus 70 ns
Minimum plus 105 ns
An RC filter may be used on the RSP pin should the need arise. A bias current of less than 8 µA flows out of the
RSP pin.
The blanking period is specified as an increase in observable minimum gate on-time. The blanking circuit, current
limit or PWM comparator, control logic, and loaded gate driver contribute to the observable current-sense loop
delay. The PWM and current limit comparators do not respond to signals shorter than 20 ns, providing some
inherent blanking within the current-sense loop delay measurement. The blanking circuit contributes almost
negligible loop delay when the BL pin is open. The blanking periods are measured as the difference between the
observed gate on-time with BL open, and its period with the BL pin connected high or low. The blanking periods
shown do not include the comparator delays.
While many converter designs do not require a resistor in series with RSP, there may be instances where one is
required to protect the pin from harmful currents. Even though the RSP pin has an absolute maximum voltage
rating of –0.3 V, the ESD clamp can withstand occasional negative current pulses, provided they are limited to
less than 100 mA. Some supply topologies, such as the self-driven synchronous rectifier circuit of Figure 38,
have the ability to drive energy back through the transformer. This causes negative voltages on RSP and
currents that can exceed the 100 mA. A small series protection resistor on RSP protects the device without
requiring a Schottky diode clamp.
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