TPS23750
TPS23770
www.ti.com
SLVS590A–JULY 2005–REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
Converter Output Stage
To V
DD
COMP
FB
Error
Amplifier
Part of TPS23750
+
1.5V
Voltage
Output
+
+
SENP
Soft
start
Translator
SEN
−
80k
1.5V
To
RTN
To PWM
Comparator
15k
15k
20k
−
RTN
MODE
Figure 32. Nonisolated Converter Configuration
Isolated PD converters that use an optocoupler, such as TL431-based circuits, should use the configuration of
Figure 33. The MODE connection disables the internal error amplifier, rendering its output high impedance. A
primary-side PWM softstart is internally implemented when the error amplifier is disabled. The same gain of
0.2 V/V appears before the PWM comparator. The COMP pin is still monitored to implement hiccup in this
configuration.
To V
PWM
Comparator
DD
From
Blanker
Part of TPS23750
Error
Amplifier
−
−
1.5V
Softstart
+
+
Soft
start
Converter Output Stage
SENP
SEN
Translator
+
−
80k
20k
+
15k
15k
Low
Voltage
Output
RSN
RTN
FB
RTN
MODE
COMP
V
BIAS
−
RTN
TLV431
Figure 33. Isolated Converter Configuration
The buck converter configuration is shown in Figure 34. The loop regulates the voltage across RLO to 1.5 V. The
translator topology provides a gain of 1 V/V from VSENP-SEN to the 15 kΩ internal series resistor. The error
amplifier gain expression is (ZCOMP-FB / 15 kΩ). The output divider and translator attenuate both the ac and dc
components, unlike the configuration of Figure 32 where the ac signal is not divided because the virtual ground
at the amplifier input cancels the effect of RLO. Addition of CBYP across RHI applies the full ac signal to the error
amplifier. The RHICBYP corner frequency should be at least an octave lower than the RZCZ zero frequency. This
method assures CBYP has little effect on standard loop design practices.
20
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