TPS23750
TPS23770
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SLVS590A–JULY 2005–REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
A class AB inverting error amplifier, with a 1.5 V fixed reference, connects between input FB and output COMP.
The error amplifier has a 1.5 MHz gain-bandwidth product and can source or sink several milliamps. This
amplifier can be disabled to allow an optocoupler feedback circuit to drive the PWM section
COMP is also the input to the current-mode PWM section. A 1/5 divider scales the COMP input to the current
comparators. Offsets built into the comparator assure that the duty cycle can be driven to 0%. The current limit
comparator threshold of 0.5 V on the RSP pin provides a regulated current limit. The fault comparator detects a
runaway condition when the peak voltage on RSP is greater than 0.75 V. This can occur with a shorted
transformer winding, a short on the switching MOSFET drain, or a shorted buck converter inductor. The
TPS23750 shuts down immediately after four consecutive fault comparator trips and enters a TMR-based hiccup
cycle.
The duty cycle is limited to 50% based on typical circuits used in PoE, providing a number of benefits. First, it
eliminates the complexity of a stabilizing current ramp. Second, it gives an assured reset period for the
magnetics. Third, many forward converters with a 1:1 reset winding require a 50% or less duty cycle. Most
applications that use a transformer or buck-mode converter prefer this lower duty cycle.
User-programmable current sense blanking eliminates the need for an RC filter. A 70 ns blanking period is
provided to serve higher-frequency switching circuits with low output-rectifier recovery periods. A 115 ns blanking
period is provided to serve medium-to-slow frequency circuits that have significant gate drive and recovery
requirements. The minimum blanking option is provided to allow short period RC filters to be used.
The TMR pin provides a closed-loop softstart when the error amplifier is used. An open-loop softstart is provided
if the internal error amplifier is disabled. TMR also implements a synthesized hiccup, or pause and restart, to limit
average power dissipation when there is a fault in the converter. Cascading failures are avoided during a fault
because the converter operates only about 9% of the time, allowing the power components to cool. A hiccup can
be triggered when the COMP pin is railed high for a programmed period, which occurs when there is an
overload, or the input voltage is too low.
The internal bias regulators eliminate external bootstrap resistors and startup regulators. The internal regulators
allow the converter to start and run as soon as inrush completes. This avoids the pitfalls associated with the
bootstrap-startup topology including failure to start and excessive startup delay.
Some PD designs use a 24 V wall adapter to operate when PoE is not available. The converter control allows
startup with at least 20.5 V applied VDD - RTN, and operation down to about 18 V.
ERROR AMPLIFIER CONNECTIONS
The TPS23750 accommodates many types of converters and feedback methods. A level translator supports a
simple low-side switch buck converter, a class-AB voltage error amplifier supports non-isolated converters, and
an error amplifier disable supports optocoupler feedback.
Some PD designers prefer to create multi-output power supplies using a flyback or forward topology, but do not
require metallic isolation between the PoE front end and the application circuits. Figure 32 shows a configuration
that enables the internal error amplifier and disables the level shifter. A standard output voltage divider and
compensation scheme utilizes the FB and COMP pins. The control loop design should account for a 0.2 V/V
attenuation factor from the error amplifier to the PWM comparator. The TMR pin ramps the reference voltage to
the error amplifier giving a closed-loop softstart.
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