Functional Description
POWER-UP
ASYNCHRONOUS OPERATION
When power is first applied, power-on reset circuitry initializ-
es the COMBO and places it into a power-down state. All
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK and MCLK must be
X
R
non-essential circuits are deactivated and the D and VF
X
O
R
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLK should be synchronous
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK /PDN pin and FS and/or FS pulses must be pres-
R
with MCLK , which is easily achieved by applying only static
X
R
X
R
ent. Thus, 2 power-down control modes are available. The
first is to pull the MCLK /PDN pin high; the alternative is to
hold both FS and FS inputs continuously lowÐthe device
logic levels to the MCLK /PDN pin. This will automatically
R
connect MCLK to all internal MCLK functions (see Pin
R
X
R
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
X
R
will power-down approximately 1 ms after the last FS or
X
FS pulse. Power-up will occur on the first FS or FS
FS starts each encoding cycle and must be synchronous
X
with MCLK and BCLK . FS starts each decoding cycle
X X R
R
X
R
pulse. The TRI-STATE PCM data output, D , will remain in
X
the high impedance state until the second FS pulse.
X
and must be synchronous with BCLK . BCLK must be a
R R
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK and BCLK may operate from
64 kHz to 2.048 MHz.
SYNCHRONOUS OPERATION
X
R
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive di-
rections. In this mode, a clock must be applied to MCLK
SHORT FRAME SYNC OPERATION
X
and the MCLK /PDN pin can be used as a power-down
R
control. A low level on MCLK /PDN powers up the device
R
and a high level powers down the device. In either case,
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
MCLK will be selected as the master clock for both the
X
transmit and receive circuits. A bit clock must also be ap-
pulses, FS and FS , must be one bit clock period long,
X R
with timing relationships specified in Figure 2. With FS high
X
plied to BCLK and the BCLK /CLKSEL can be used to
R
during a falling edge of BCLK , the next rising edge of
X
X
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
BCLK enables the D TRI-STATE output buffer, which will
X X
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge dis-
ables the D output. With FS high during a falling edge of
X
R
BCLK (BCLK in synchronous mode), the next falling edge
X
of BCLK latches in the sign bit. The following seven falling
R
edges latch in the seven remaining bits. All four devices
may utilize the short frame sync pulse in synchronous or
asynchronous operating mode.
R
With a fixed level on the BCLK /CLKSEL pin, BCLK will be
X
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
R
which can be selected, depending on the state of BCLK
/
R
CLKSEL. In this synchronous mode, the bit clock, BCLK ,
X
may be from 64 kHz to 2.048 MHz, but must be synchro-
LONG FRAME SYNC OPERATION
nous with MCLK .
X
To use the long frame mode, both the frame sync pulses,
FS and FS , must be three or more bit clock periods long,
Each FS pulse begins the encoding cycle and the PCM
X
data from the previous encode cycle is shifted out of the
X
R
with timing relationships specified in Figure 3. Based on the
enabled D output on the positive edge of BCLK . After 8
X
X
bit clock periods, the TRI-STATE D output is returned to a
transmit frame sync, FS , the COMBO will sense whether
X
X
high impedance state. With an FS pulse, PCM data is
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a mini-
mum of 160 ns. The D TRI-STATE output buffer is enabled
R
latched via the D input on the negative edge of BCLK (or
R
X
BCLK if running). FS and FS must be synchronous with
X
R
X
R
with the rising edge of FS or the rising edge of BCLK ,
X
X
MCLK
.
X/R
whichever comes later, and the first bit clocked out is the
sign bit. The following seven BCLK rising edges clock out
the remaining seven bits. The D output is disabled by the
X
TABLE I. Selection of Master Clock Frequencies
Master Clock
X
falling BCLK edge following the eighth rising edge, or by
X
FS going low, whichever comes later. A rising edge on the
X
receive frame sync pulse, FS , will cause the PCM data at
Frequency Selected
BCLK /CLKSEL
R
R
TP3057
TP3054
D
to be latched in on the next eight falling edges of BCLK
R
R
(BCLK in synchronous mode). All four devices may utilize
X
the long frame sync pulse in synchronous or asynchronous
mode.
Clocked
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
0
1
1.536 MHz or
1.544 MHz
2.048 MHz
In applications where the LSB bit is used for signalling with
FS two bit clock periods long, the decoder will interpret the
R
lost LSB as ‘‘(/2’’ to minimize noise and distortion.
1.536 MHz or
1.544 MHz
3
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