Block Diagram
FIGURE 1
TL/H/5510–2
Pin Description
Symbol
Function
Negative power supply pin.
e b
Symbol
Function
should be synchronous with MCLK for best per-
V
BB
X
g
V
BB
5V 5%.
formance. When MCLK is connected continu-
R
ously low, MCLK is selected for all internal tim-
X
GNDA
Analog ground. All signals are referenced
to this pin.
ing. When MCLK is connected continuously
R
high, the device is powered down.
VF
O
Analog output of the receive power ampli-
fier.
R
MCLK
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asynchronous
X
V
CC
Positive power supply pin.
with MCLK . Best performance is realized from
R
synchronous operation.
e a
g
V
5V 5%.
Receive frame sync pulse which enables
BCLK to shift PCM data into D . FS is
CC
FS
R
FS
Transmit frame sync pulse input which enables
BCLK to shift out the PCM data on D . FS is
X
R
R
R
X
X
X
an 8 kHz pulse train. See Figures 2 and 3
for timing details.
an 8 kHz pulse train, see Figures 2 and 3 for
timing details.
D
Receive data input. PCM data is shifted
into D following the FS leading edge.
R
BCLK
The bit clock which shifts out the PCM data on
D . May vary from 64 kHz to 2.048 MHz, but
X
R
R
X
BCLK /CLKSEL The bit clock which shifts data into D af-
R
R
must be synchronous with MCLK .
X
ter the FS leading edge. May vary from
R
64 kHz to 2.048 MHz. Alternatively, may
D
X
The TRI-STATE PCM data output which is en-
É
abled by FS .
X
be a logic input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
TS
Open drain output which pulses low during the
encoder time slot.
X
BCLK is used for both transmit and re-
X
ceive directions (see Table I).
GS
X
Analog output of the transmit input amplifier.
Used to externally set gain.
MCLK /PDN
R
Receive master clock. Must be
1.536 MHz, 1.544 MHz or 2.048 MHz.
May be asynchronous with MCLK , but
VF Ib
X
Inverting input of the transmit input amplifier.
VF Ia
Non-inverting input of the transmit input amplifi-
er.
X
X
2
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