e
Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
e
0 C to 70 C by correlation with 100% electrical testing at T 25 C. All other limits are
A
e b
e
g
g
5.0V 5%, V
5.0V 5%; T
§
§
§
BB
A
assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA.
e
e
e b
e
0.7V. See Definitions and Timing Conventions section for test methods information.
e
Typicals specified at V
CC
5.0V, V
BB
5.0V, T
25 C. All timing parameters are measured at V
2.0V and V
§
A
OH
OL
Symbol
1/t
Parameter
Conditions
Min
Typ
Max
Units
Frequency of Master Clocks
Depends on the Device Used and the
1.536
1.544
MHz
MHz
MHz
PM
BCLK /CLKSEL Pin.
R
MCLK and MCLK
X
2.048
R
R
R
t
t
t
t
t
t
t
t
Rise Time of Master Clock
Fall Time of Master Clock
Period of Bit Clock
MCLK and MCLK
X
50
50
ns
ns
ns
ns
ns
ns
ns
ns
RM
MCLK and MCLK
X
FM
485
488
15725
50
PB
Rise Time of Bit Clock
Fall Time of Bit Clock
BCLK and BCLK
X R
RB
BCLK and BCLK
R
50
FB
X
Width of Master Clock High
Width of Master Clock Low
MCLK and MCLK
X
160
160
100
WMH
WML
SBFM
R
R
MCLK and MCLK
X
Set-Up Time from BCLK High
X
First Bit Clock after the Leading
Edge of FS
to MCLK Falling Edge
X
X
t
Set-Up Time from FS High
X
Long Frame Only
100
ns
SFFM
to MCLK Falling Edge
X
e
IH
t
t
t
Width of Bit Clock High
Width of Bit Clock Low
V
2.2V
160
160
0
ns
ns
ns
WBH
WBL
HBFL
e
V
IL
0.6V
Holding Time from Bit Clock
Low to Frame Sync
Long Frame Only
Short Frame Only
Long Frame Only
t
t
t
Holding Time from Bit Clock
High to Frame Sync
0
80
0
ns
ns
ns
HBFS
SFB
Set-Up Time from Frame Sync
to Bit Clock Low
e
Load 150 pF plus 2 LSTTL Loads
Delay Time from BCLK High
X
to Data Valid
140
DBD
e
Load 150 pF plus 2 LSTTL Loads
t
t
Delay Time to TS Low
X
140
165
ns
ns
DBTS
e
Delay Time from BCLK Low to
X
Data Output Disabled
C
L
0 pF to 150 pF
50
20
DZC
e
t
Delay Time to Valid Data from
C
L
0 pF to 150 pF
165
ns
DZF
FS or BCLK , Whichever
X X
Comes Later
t
t
t
t
t
Set-Up Time from D Valid to
R
50
50
ns
ns
ns
ns
ns
SDB
HBD
SF
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low to
D
R
Invalid
Set-Up Time from FS
X/R
to
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
BCLK Low
X/R
Hold Time from BCLK
X/R
Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
100
HF
to FS
X/R
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
HBFl
(FS or FS
X
)
R
t
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
WFL
6
TI [ TEXAS INSTRUMENTS ]
