TMS570LS3137
SPNS162.–SEPTEMBER 2011
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Table 3-2. Output Buffer Drive Strengths (continued)
Low-level Output Current,
IOL for VI=VOLmax
or
Signals
High-level Output Current,
IOH for VI=VOHmin
TEST,
4mA
MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,
nRST
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC,
GIOA[0-7], GIOB[0-7],
LINRX, LINTX,
2mA zero-dominant
MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA,
MIBSPI5NCS[0-3], MIBSPI5NENA,
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],
N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14],
N2HET2[15], N2HET2[16], N2HET2[18],
SPI2NCS[0], SPI2NENA, SPI4NCS[0], SPI4NENA
ECLK,
selectable 8mA / 2mA
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8mA for these signals.
3.8 Input Timings
tpw
VCCIO
Input
VIH
VIH
VIL
VIL
0
Figure 3-2. TTL-Level Inputs
Table 3-3. Timing Requirements for Inputs(1)
Parameter
MIN
tc(VCLK) + 10(2)
MAX
Unit
tpw
Input minimum pulse width
ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown above is only valid for pin used in GIO mode.
46
Device Operating Conditions
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