TMS570LS3137
SPNS162.–SEPTEMBER 2011
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tr
t
f
VCCIO
Output
VOH
VOH
VOL
VOL
0
Figure 3-3. CMOS-Level Outputs
Table 3-5. Timing Requirements for Outputs(1)
Parameter
MIN
MAX
UNIT
td(parallel_out)
Delay between low to high, or high to low transition of general-purpose output signals
that can be configured by an application in parallel, e.g. all signals in a GIOA port, or
all N2HET1 signals, etc.
5
ns
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 3-2 for output buffer drive strength information on each signal.
48
Device Operating Conditions
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