www.ti.com
SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
System Control Block
C28x CPU
I2CAENCLK
SYSCLKOUT
Control
Data[16]
SDAA
GPIO
MUX
I2C-A
SCLA
I2CINT1A
Data[16]
Addr[16]
I2CINT2A
PIE
Block
A.
B.
The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-15. I2C Peripheral Module Interfaces
The registers in
configure and control the I2C port operation.
Table 4-14. I2C-A Registers
NAME
I2COAR
I2CIER
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
-
-
I2C own address register
I2C interrupt enable register
I2C status register
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
DESCRIPTION
Copyright © 2003–2011, Texas Instruments Incorporated
Peripherals
Peripheral Bus
SYSRS
81
Product Folder Link(s):
TI [ TEXAS INSTRUMENTS ]
