TMS320F2808PZA 参数 Datasheet PDF下载

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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011

The SPI port operation is configured and controlled by the registers listed in

through

Table 4-10. SPI-A Registers

NAME

SPICCR

SPICTL

SPISTS

SPIBRR

SPIRXEMU

SPIRXBUF

SPITXBUF

SPIDAT

SPIFFTX

SPIFFRX

SPIFFCT

SPIPRI

(1)

ADDRESS

0x7040

0x7041

0x7042

0x7044

0x7046

0x7047

0x7048

0x7049

0x704A

0x704B

0x704C

0x704F

SIZE (x16)

1

1

1

1

1

1

1

1

1

1

1

1

DESCRIPTION

(1)

SPI-A Configuration Control Register

SPI-A Operation Control Register

SPI-A Status Register

SPI-A Baud Rate Register

SPI-A Receive Emulation Buffer Register

SPI-A Serial Input Buffer Register

SPI-A Serial Output Buffer Register

SPI-A Serial Data Register

SPI-A FIFO Transmit Register

SPI-A FIFO Receive Register

SPI-A FIFO Control Register

SPI-A Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

Table 4-11. SPI-B Registers

NAME

SPICCR

SPICTL

SPISTS

SPIBRR

SPIRXEMU

SPIRXBUF

SPITXBUF

SPIDAT

SPIFFTX

SPIFFRX

SPIFFCT

SPIPRI

(1)

ADDRESS

0x7740

0x7741

0x7742

0x7744

0x7746

0x7747

0x7748

0x7749

0x774A

0x774B

0x774C

0x774F

SIZE (x16)

1

1

1

1

1

1

1

1

1

1

1

1

DESCRIPTION

(1)

SPI-B Configuration Control Register

SPI-B Operation Control Register

SPI-B Status Register

SPI-B Baud Rate Register

SPI-B Receive Emulation Buffer Register

SPI-B Serial Input Buffer Register

SPI-B Serial Output Buffer Register

SPI-B Serial Data Register

SPI-B FIFO Transmit Register

SPI-B FIFO Receive Register

SPI-B FIFO Control Register

SPI-B Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

Copyright © 2003–2011, Texas Instruments Incorporated

Peripherals

77

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