TMS320F2808PZA 参数 Datasheet PDF下载

www.ti.com

SPRS230M – OCTOBER 2003 – REVISED MARCH 2011

The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1

to enable 32-bit operations on the registers (along with 16-bit operations).

shows the GPIO

register mapping.

Table 4-15. GPIO Registers

NAME

GPACTRL

GPAQSEL1

GPAQSEL2

GPAMUX1

GPAMUX2

GPADIR

GPAPUD

Reserved

GPBCTRL

GPBQSEL1

GPBQSEL2

GPBMUX1

GPBMUX2

GPBDIR

GPBPUD

Reserved

Reserved

ADDRESS

0x6F80

0x6F82

0x6F84

0x6F86

0x6F88

0x6F8A

0x6F8C

0x6F8E –

0x6F8F

0x6F90

0x6F92

0x6F94

0x6F96

0x6F98

0x6F9A

0x6F9C

0x6F9E –

0x6F9F

0x6FA0 –

0x6FBF

0x6FC0

0x6FC2

0x6FC4

0x6FC6

0x6FC8

0x6FCA

0x6FCC

0x6FCE

0x6FD0 –

0x6FDF

0x6FE0

0x6FE1

0x6FE2

0x6FE3 –

0x6FE7

0x6FE8

0x6FEA –

0x6FFF

SIZE (x16)

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

32

DESCRIPTION

GPIO A Control Register (GPIO0 to 31)

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPIO A MUX 1 Register (GPIO0 to 15)

GPIO A MUX 2 Register (GPIO16 to 31)

GPIO A Direction Register (GPIO0 to 31)

GPIO A Pull Up Disable Register (GPIO0 to 31)

Reserved

GPIO B Control Register (GPIO32 to 35)

GPIO B Qualifier Select 1 Register (GPIO32 to 35)

Reserved

GPIO B MUX 1 Register (GPIO32 to 35)

Reserved

GPIO B Direction Register (GPIO32 to 35)

GPIO B Pull Up Disable Register (GPIO32 to 35)

Reserved

Reserved

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

GPADAT

GPASET

GPACLEAR

GPATOGGLE

GPBDAT

GPBSET

GPBCLEAR

GPBTOGGLE

Reserved

2

2

2

2

2

2

2

2

16

GPIO Data Register (GPIO0 to 31)

GPIO Data Set Register (GPIO0 to 31)

GPIO Data Clear Register (GPIO0 to 31)

GPIO Data Toggle Register (GPIO0 to 31)

GPIO Data Register (GPIO32 to 35)

GPIO Data Set Register (GPIO32 to 35)

GPIO Data Clear Register (GPIO32 to 35)

GPIO Data Toggle Register (GPIO32 to 35)

Reserved

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL

GPIOXINT2SEL

GPIOXNMISEL

Reserved

GPIOLPMSEL

Reserved

1

1

1

5

2

22

XINT1 GPIO Input Select Register (GPIO0 to 31)

XINT2 GPIO Input Select Register (GPIO0 to 31)

XNMI GPIO Input Select Register (GPIO0 to 31)

Reserved

LPM GPIO Select Register (GPIO0 to 31)

Reserved

Copyright © 2003–2011, Texas Instruments Incorporated

Peripherals

83

Product Folder Link(s):