TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
Table 8-6. EDMA3 Transfer Controller 1 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
SADST
REGISTER NAME
Source Active Destination Address Register
02A2 824C
02A2 8250
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A2 8254
02A2 8258
02A2 825C
02A2 8260
02A2 8264 - 02A2 827C
02A2 8280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A2 8284
02A2 8288
02A2 828C - 02A2 82FC
02A2 8300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
02A2 8304
02A2 8308
02A2 830C
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
02A2 8310
02A2 8314
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A2 8318 - 02A2 833C
02A2 8340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
02A2 8344
02A2 8348
02A2 834C
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
02A2 8350
02A2 8354
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A2 8358 - 02A2 837C
02A2 8380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
02A2 8384
02A2 8388
02A2 838C
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
02A2 8390
02A2 8394
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A2 8398 - 02A2 83BC
02A2 83C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
02A2 83C4
02A2 83C8
02A2 83CC
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
02A2 83D0
02A2 83D4
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A2 83D8 - 02A2 FFFC
Table 8-7. EDMA3 Transfer Controller 2 Registers
HEX ADDRESS RANGE
02A3 0000
ACRONYM
REGISTER NAME
PID
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A3 0004
TCCFG
02A3 0008 - 02A3 00FC
02A3 0100
-
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A3 0104 - 02A3 011C
96
Peripheral Information and Electrical Specifications
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