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TMS320TCI6487 参数 Datasheet PDF下载

TMS320TCI6487图片预览
型号: TMS320TCI6487
PDF下载: 下载PDF文件 查看货源
内容描述: 通信基础设施数字信号处理器 [Communications Infrastructure Digital Signal Processor]
分类和应用: 数字信号处理器通信
文件页数/大小: 206 页 / 2183 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320TCI6487  
TMS320TCI6488  
Communications Infrastructure Digital Signal Processor  
www.ti.com  
SPRS358FAPRIL 2007REVISED AUGUST 2008  
Table 2-5. Terminal Functions (continued)  
SIGNAL  
NAME  
TYPE(1) IPD/IPU(2)  
SIGNAL DESCRIPTION  
NO.  
GENERAL PURPOSE INPUT/OUTPUT (GPIO)  
IPD  
GP00  
GP01  
GP02  
GP03  
GP04  
GP05  
GP06  
GP07  
GP08  
GP09  
GP10  
GP11  
GP12  
GP13  
GP14  
GP15  
T3  
U4  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
IPD  
IPD  
IPD  
IPU  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
V1  
U3  
General Purpose Input/Output  
T4  
GPIO[3:0] are mapped to BOOTMODE[3:0]  
(see Section 2.4.1, Boot Modes Supported)  
GPIO4 is mapped to LENDIAN  
0 = Big Endian  
V2  
V3  
1 = Little Endian (default)  
Y3  
GPIO5 is mapped to L2_CONFIG  
0 = Asymmetric L2 Configuration (default)  
1 = Symmetric L2 Configuration  
GPIO[7:6] are not multiplexed  
GPIO[11:8] are mapped to DEVNUM[3:0]  
(see Section 2.4.1, Boot Modes Supported)  
GPIO[15:12] are not multiplexed  
Y4  
AA2  
AA3  
AB4  
AB3  
AB2  
AA4  
AC3  
I2C  
SCL  
SDA  
E4  
D4  
I/O/Z  
I/O/Z  
I2C Clock (open drain)  
I2C Data (open drain)  
MULTICHANNEL BUFFERED SERIAL PORT (McBSP)  
CLKS0  
CLKR0  
CLKX0  
DR0  
D20  
B20  
C20  
A20  
D19  
B21  
A21  
A25  
A24  
C22  
D21  
B22  
C21  
A22  
I
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
McBSP0 Module Clock  
McBSP0 Receive Clock  
McBSP0 Transmit Clock  
McBSP0 Receive Data  
McBSP0 Transmit Data  
McBSP0 Receive Frame Sync  
McBSP0 Transmit Frame Sync  
McBSP1 Module Clock  
McBSP1 Receive Clock  
McBSP1 Transmit Clock  
McBSP1 Receive Data  
McBSP1 Transmit Data  
McBSP1 Receive Frame Sync  
McBSP1 Transmit Frame Sync  
MISCELLANEOUS  
I/O/Z  
I/O/Z  
I
DX0  
O/Z  
I/O/Z  
I/O/Z  
I
FSR0  
FSX0  
CLKS1  
CLKR1  
CLKX1  
DR1  
I/O/Z  
I/O/Z  
I
DX1  
O/Z  
I/O/Z  
I/O/Z  
FSR1  
FSX1  
VCNTL0  
VCNTL1  
VCNTL2  
VCNTL3  
G3  
G2  
H4  
H3  
O
O
O
O
Voltage Control Outputs to variable core power supply (open-drain buffers)  
Note: These pins must be externally pulled up. For more infomation, see the  
TMS320TCI6488 Hardware Design Guide application report (literature number  
SPRAAG5).  
SERIAL RAPIDIO (SRIO)  
RIORXN0  
RIORXP0  
RIORXN1  
RIORXP1  
A9  
I
I
I
I
A10  
A13  
A12  
Serial RapidIO Receive Data (2 links)  
Submit Documentation Feedback  
Device Overview  
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