TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
8.21 Antenna Interface Subsystem
The Antenna Interface Subsystem (AIF) consists of the Antenna Interface module and two SERDES
macros. The AIF relies on the performance SerDes macro (high-speed serial link) with a logic layer for the
OBSAI RP3 and CPRI protocols. The AIF is used to connect to the backplane for transmission and
reception of antenna data, as well as to additional device peripherals.
The AIF supports OBSAI/CPRI daisy chaining between DSPs:
•
•
OBSAI - 768Mbps, 1.536Gbps, 3.072Gbps link rates supported
CPRI - 614.4Mbps, 1.2288Gbps, 2.4576Gbps link rates supported
OBSAI and CPRI standards compliant antenna interface
•
6 configurable (Full Duplex) high-speed serial links in either OBSAI or CPRI modes that can support a
variety of data rates:
•
•
•
•
Supports star or daisy chain topologies.
Each link can be used for uplink or downlink.
Multiple slower links can be combined into faster speed links.
Controls Word content supplied via DSP software.
The AIF is a slave peripheral, accepting all transactions from the DMA switch fabric, providing uplink data
to the front end interface (FEI) of the receive accelerator block (RAC) or to device memory and
transmitting downlink, delayed stream, and PIC data from device memory. Each link of the antenna
interface includes a differential receive and transmit signal pair.
Table 8-77. AIF Receive and Transmit Signal Pairs
PIN NAMES
AIFTXN [5:0]
AIFTXP [5:0]
AIFRXN [5:0]
AIFRXP [5:0]
I/O
OUT
OUT
IN
NUMBER
DESCRIPTION
6
6
6
6
Antenna Interface Links 0-5 Transmit (Neg) Data Lines.
Antenna Interface Links 0-5 Transmit (Pos) Data Lines.
Antenna Interface Links 0-5 Receive (Neg) Data Lines.
Antenna Interface Links 0-5 Receive (Pos) Data Lines.
IN
8.21.1 Antenna Interface System (AIF) Register Description(s)
Table 8-78. Antenna Interface System Registers
HEX ADDRESS
02BC 0000
ACRONYM
AIF_PD
REGISTER NAME
AI Peripheral ID
02BC 0004
AIF_GLOBAL_CFG
AIF_EMU_CNTL
VC_BUS_ERR
-
AI Global Configuration
AI Emulation Control
VC Bus Error Register
Reserved
02BC 0008
02BC 000C
02BC 0010 - 02BC 2FFC
02BC 3000
CD_OUT_MUX_SEL_CFG
Combiner - Decombiner Output Mux Select Config
Register 0
02BC 3004
02BC 3008
CD_CB_SRC_SEL_CFG
Combiner Source Select Config Register
Combiner Alignment Offset Config Register
Combiner Valid Window Config Register
Decombiner Source Select Config Register
Decombiner Destination Select Config Register
Reserved
CD_CB_OFFSET_CFG
02BC 300C
CD_CB_VALID_WIND_CFG
02BC 3010
CD_DC_SRC_SEL_CFG
02BC 3014
CD_DC_DST_SEL_CFG
02BC 3018 - 02BC 307C
02BC 3080
-
CD_STS
Combiner - Decombiner Status Register
Reserved
02BC 3084 - 02BC 3FFC
02BC 4000
-
LINK0_CFG
-
Link 0 Configuration Register
Reserved
02BC 4004 - 02BC 47FC
184
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
TI [ TEXAS INSTRUMENTS ]
