TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
Table 8-68. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 085C
02D0 08560
02D0 0864
02D0 0868
02D0 086C
02D0 0870
02D0 0874
02D0 0878
02D0 087C
02D0 0880
02D0 0884
02D0 0888
02D0 088C
02D0 0890
02D0 0894
02D0 0898
02D0 089C
02D0 08A0
02D0 08A4
02D0 08A8
02D0 08AC
02D0 08B0
02D0 08B4
02D0 08B8
02D0 08BC
02D0 08C0
02D0 08C4
02D0 08C8
02D0 08CC
02D0 08D0
02D0 08D4
02D0 08D8
02D0 08DC
02D0 08E0
02D0 08E4
02D0 08E8
02D0 08EC
02D0 08F0
02D0 08F4
02D0 08F8
02D0 08FC
02D0 0900
02D0 0904
02D0 0908
02D0 090C
02D0 0910
02D0 0914
ACRONYM
REGISTER NAME
Mailbox-to-Queue Mapping Register H11
Mailbox-to-Queue Mapping Register L12
Mailbox-to-Queue Mapping Register H12
Mailbox-to-Queue Mapping Register L13
Mailbox-to-Queue Mapping Register H13
Mailbox-to-Queue Mapping Register L14
Mailbox-to-Queue Mapping Register H14
Mailbox-to-Queue Mapping Register L15
Mailbox-to-Queue Mapping Register H15
Mailbox-to-Queue Mapping Register L16
Mailbox-to-Queue Mapping Register H16
Mailbox-to-Queue Mapping Register L17
Mailbox-to-Queue Mapping Register H17
Mailbox-to-Queue Mapping Register L18
Mailbox-to-Queue Mapping Register H18
Mailbox-to-Queue Mapping Register L19
Mailbox-to-Queue Mapping Register H19
Mailbox-to-Queue Mapping Register L20
Mailbox-to-Queue Mapping Register H20
Mailbox-to-Queue Mapping Register L21
Mailbox-to-Queue Mapping Register H21
Mailbox-to-Queue Mapping Register L22
Mailbox-to-Queue Mapping Register H22
Mailbox-to-Queue Mapping Register L23
Mailbox-to-Queue Mapping Register H23
Mailbox-to-Queue Mapping Register L24
Mailbox-to-Queue Mapping Register H24
Mailbox-to-Queue Mapping Register L25
Mailbox-to-Queue Mapping Register H25
Mailbox-to-Queue Mapping Register L26
Mailbox-to-Queue Mapping Register H26
Mailbox-to-Queue Mapping Register L27
Mailbox-to-Queue Mapping Register H27
Mailbox-to-Queue Mapping Register L28
Mailbox-to-Queue Mapping Register H28
Mailbox-to-Queue Mapping Register L29
Mailbox-to-Queue Mapping Register H29
Mailbox-to-Queue Mapping Register L30
Mailbox-to-Queue Mapping Register H30
Mailbox-to-Queue Mapping Register L31
Mailbox-to-Queue Mapping Register H31
Flow Control Table Entry Register 0
RXU_MAP_H11
RXU_MAP_L12
RXU_MAP_H12
RXU_MAP_L13
RXU_MAP_H13
RXU_MAP_L14
RXU_MAP_H14
RXU_MAP_L15
RXU_MAP_H15
RXU_MAP_L16
RXU_MAP_H16
RXU_MAP_L17
RXU_MAP_H17
RXU_MAP_L18
RXU_MAP_H18
RXU_MAP_L19
RXU_MAP_H19
RXU_MAP_L20
RXU_MAP_H20
RXU_MAP_L21
RXU_MAP_H21
RXU_MAP_L22
RXU_MAP_H22
RXU_MAP_L23
RXU_MAP_H23
RXU_MAP_L24
RXU_MAP_H24
RXU_MAP_L25
RXU_MAP_H25
RXU_MAP_L26
RXU_MAP_H26
RXU_MAP_L27
RXU_MAP_H27
RXU_MAP_L28
RXU_MAP_H28
RXU_MAP_L29
RXU_MAP_H29
RXU_MAP_L30
RXU_MAP_H30
RXU_MAP_L31
RXU_MAP_H31
FLOW_CNTL0
FLOW_CNTL1
FLOW_CNTL2
FLOW_CNTL3
FLOW_CNTL4
FLOW_CNTL5
Flow Control Table Entry Register 1
Flow Control Table Entry Register 2
Flow Control Table Entry Register 3
Flow Control Table Entry Register 4
Flow Control Table Entry Register 5
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Peripheral Information and Electrical Specifications
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