TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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Table 8-68. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 06A0
ACRONYM
REGISTER NAME
RapidIO Queue8 RX DMA Completion Pointer Register
RIO_Queue8_RxDMA_CP
RIO_Queue9_RxDMA_CP
RIO_Queue10_RxDMA_CP
RIO_Queue11_RxDMA_CP
RIO_Queue12_RxDMA_CP
RIO_Queue13_RxDMA_CP
RIO_Queue14_RxDMA_CP
RIO_Queue15_RxDMA_CP
-
02D0 06A4
RapidIO Queue9 RX DMA Completion Pointer Register
RapidIO Queue10 RX DMA Completion Pointer Register
RapidIO Queue11 RX DMA Completion Pointer Register
RapidIO Queue12 RX DMA Completion Pointer Register
RapidIO Queue13 RX DMA Completion Pointer Register
RapidIO Queue14 RX DMA Completion Pointer Register
RapidIO Queue15 RX DMA Completion Pointer Register
Reserved
02D0 0648
02D0 06AC
02D0 06B0
02D0 06B4
02D0 06B8
02D0 06BC
02D0 06C0 - 02D0 06FC
02D0 0700
RIO_TXQUEUE_TEAR_DOWN
RIO_TX_CPPI_FLOW_MASKS0
RIO_TX_CPPI_FLOW_MASKS1
RIO_TX_CPPI_FLOW_MASKS2
RIO_TX_CPPI_FLOW_MASKS3
RIO_TX_CPPI_FLOW_MASKS4
-
RapidIO TX Queue Tear Down Register
RapidIO TX CPPI Support Flow Masks 0 Register
RapidIO TX CPPI Support Flow Masks 1 Register
RapidIO TX CPPI Support Flow Masks 2 Register
RapidIO TX CPPI Support Flow Masks 3 Register
RapidIO TX CPPI Support Flow Masks 4 Register
Reserved
02D0 0704
02D0 0708
02D0 070C
02D0 0710
02D0 0714
02D0 0718 - 02D0 073C
02D0 0740
RIO_RX_QUEUE_TEAR_DOWN
RIO_RX_CPPI_CNTL
-
RapidIO RX Queue Tear Down Register
RapidIO CPPI Control Register
02D0 0744
02D0 0748 - 02D0 07DC
02D0 07E0
Reserved
RIO_TX_QUEUE_CNTL0
RIO_TX_QUEUE_CNTL1
RIO_TX_QUEUE_CNTL2
RIO_TX_QUEUE_CNTL3
-
RapidIO TX Queue Control 0 Register
RapidIO TX Queue Control 1 Register
RapidIO TX Queue Control 2 Register
RapidIO TX Queue Control 3 Register
Reserved
02D0 07E4
02D0 07E8
02D0 07EC
02D0 07F0 - 02D0 07FC
02D0 0800
RXU_MAP_L0
Mailbox-to-Queue Mapping Register L0
Mailbox-to-Queue Mapping Register H0
Mailbox-to-Queue Mapping Register L1
Mailbox-to-Queue Mapping Register H1
Mailbox-to-Queue Mapping Register L2
Mailbox-to-Queue Mapping Register H2
Mailbox-to-Queue Mapping Register L3
Mailbox-to-Queue Mapping Register H3
Mailbox-to-Queue Mapping Register L4
Mailbox-to-Queue Mapping Register H4
Mailbox-to-Queue Mapping Register L5
Mailbox-to-Queue Mapping Register H5
Mailbox-to-Queue Mapping Register L6
Mailbox-to-Queue Mapping Register H6
Mailbox-to-Queue Mapping Register L7
Mailbox-to-Queue Mapping Register H7
Mailbox-to-Queue Mapping Register L8
Mailbox-to-Queue Mapping Register H8
Mailbox-to-Queue Mapping Register L9
Mailbox-to-Queue Mapping Register H9
Mailbox-to-Queue Mapping Register L10
Mailbox-to-Queue Mapping Register H10
Mailbox-to-Queue Mapping Register L11
02D0 0804
RXU_MAP_H0
02D0 0808
RXU_MAP_L1
02D0 080C
02D0 0810
RXU_MAP_H1
RXU_MAP_L2
02D0 0814
RXU_MAP_H2
02D0 0818
RXU_MAP_L3
02D0 081C
02D0 0820
RXU_MAP_H3
RXU_MAP_L4
02D0 0824
RXU_MAP_H4
02D0 0828
RXU_MAP_L5
02D0 082C
02D0 0830
RXU_MAP_H5
RXU_MAP_L6
02D0 0834
RXU_MAP_H6
02D0 0838
RXU_MAP_L7
02D0 083C
02D0 0840
RXU_MAP_H7
RXU_MAP_L8
02D0 0844
RXU_MAP_H8
02D0 0848
RXU_MAP_L9
02D0 084C
02D0 0850
RXU_MAP_H9
RXU_MAP_L10
02D0 0854
RXU_MAP_H10
02D0 0858
RXU_MAP_L11
170
Peripheral Information and Electrical Specifications
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