TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.15.2 VCP2 Peripheral Register Description(s)
Table 8-66. VCP2 Registers
EDMA BUS HEX ADDRESS RANGE
CONFIGURATION BUS HEX
ACRONYM
REGISTER NAME
ADDRESS RANGE
5800 0000
5800 0004
-
VCPIC0
VCPIC1
VCPIC2
VCPIC3
VCPIC4
VCPIC5
-
VCP2 input configuration Register 0
VCP2 input configuration Register 1
VCP2 input configuration Register 2
VCP2 input configuration Register 3
VCP2 input configuration Register 4
VCP2 Input Configuration Register 5
Reserved
-
5800 0008
-
5800 000C
-
5800 0010
-
5800 0014
-
5800 0018 - 5800 0044
5800 0048
-
-
VCPOUT0
VCPOUT1
-
VCP2 output Register 0
5800 004C
-
-
VCP2 output Register 1
5800 0050 - 5800 007C
5800 0080
Reserved
N/A
VCPWBM
VCP2 branch metrics write FIFO
Register
5800 0084 - 5800 009C
-
-
VCPRDECS
VCPEXE
VCPEND
VCPSTAT0
VCPSTAT1
VCPERR
-
Reserved
5800 00C0
N/A
N/A
VCP2 decisions read FIFO Register
VCP2 execution Register
VCP2 Endian mode Register
VCP2 Status Register 0
VCP2 Status Register 1
VCP2 error Register
Reserved
02B8 0018
N/A
02B8 0020
N/A
02B8 0040
N/A
02B8 0044
N/A
02B8 0050
-
-
N/A
02B8 0060
VCPEMU
-
VCP2 emulation control Register
Reserved
N/A
02B8 0064 - 02B9 FFFF
5800 1000
5800 2000
5800 3000
5800 6000
5800 F000
-
-
-
-
-
BM
Branch metrics
SM
State metric
TBHD
Traceback hard decision
Traceback soft decision
Decoded bits
TBSD
IO
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Peripheral Information and Electrical Specifications
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